ARM7TDMI System Peripherals - Atmel Corporation

Features

•Atmel Advanced System Bus (ASB) Arbitration

•Customized Options

– Number of Masters (2 to 7)

– Priority of Masters

– Possibility of Inserting Master Hand-over Cycle for Each Master

•Atmel AMBA™ Master Compliant

•Fully Scan Testable up to 96% Fault Coverage

Description

The Advanced System Bus (ASB), part of the Advanced Microcontroller Bus Architec-

ture (AMBA), supports the connection of multiple processors. Therefore, it requires an

arbiter to ensure that only one bus master has write access to the ASB at any particu-

lar point in time. Each bus master can request the bus; the Arbiter decides which

master has the highest priority and issues a grant accordingly. A hand-over cycle is

inserted if required.

Each master is connected to the Arbiter via two signals:

• A request signal areq: output from the master, input to the arbiter

• A grant signal agnt: input to the master, output from the arbiter

For further information on the AMBA structure, Master Signals Manager and Read

Data Manager, refer to the ARM7TDMI™ System Architecture datasheet, Literature

Number 1353.

Figure 1. Arbiter Symbol

Scan Test Configuration

The coverage is maximum if all non-scan inputs can be controlled and all non-scan

outputs can be observed. In order to achieve this, the ATPG vectors must be gener-

ated on the entire circuit (top level) which includes the Arbiter or all Arbiter I/Os must

have a top-level access and ATPG vectors must be applied to these pins.

scan_test_mode

Arbiter

AMBA Bus

Inputs agnt[N-1:0]

blok[N-1:0]

nreset_f

areq[N-1:0]

nclock AMBA Bus

Output

Scan Test test_si

test_se

test_so

32-bit

Embedded Core

Peripheral

Arbiter

Rev. 1284D–03/01

2Arbiter

1284D–03/01

Notes: 1. N = Number of masters

2. The scan chain uses the clock nclock.

Table 1. Pin Description

Name Type Source/Destination Description

AMBA Bus Inputs

nreset_f Input From Reset Controller System reset for parts synchronized on the falling edge of the ASB

clock (nclock). Active low.

nclock Input ASB system clock.

blok[N(1)-1:0] Input From Masters Locked transfers. Active high.

areq[N(1)-1:0] Input From Masters Bus request. Each master has a corresponding areq signal. Active

high.

agnt[N(1)-1:0] Output To Masters Bus grant. Each master has a corresponding agnt signal. Active

high.

Scan Test

scan_test_mode Input For scan test only. This input must be set to 1 only during scan test.

Must be set to 0 in normal operating mode.

test_se Input Test scan shift enabled when tied to 1.

test_si(2) Input Test scan input (input of the scan chain).

test_so(2) Output Test scan output (output of the scan chain).

Arbiter

1284D–03/01

Operating in an

AMBA System

Figure 2. AMBA Data Buses

brdata

BD_from_masters

BD_from_APB

BDout

ARM Memory

Controller

(including Decoder,

EBI and ARAM

Controller)

bwait_from_APB

bwait_to_ASB

wait_1C

data_to_master

pdc_data

data_from_masters

APB

Peripherals

Bridge

areq

agnt

bwait_in bwdata

Arbiter

(N masters)

agnt[N-1]

areq[N-1]

pdc_sel_bridge

ARM7TDMI

Core and Wrapper

bridge_sel

Advanced System

Bus (ASB)

Advanced Peripheral

Bus (APB)

dsel_bridge

Read

Data

Manager

Master

Signals

Manager

agnt[i]

areq[i]

bwait_in bwdata

brdata

agnt

areq

Master[i]

(DOUT on

ARM Core)

(DIN on

ARM Core)

4Arbiter

1284D–03/01

Figure 3. Master Control Signals

blok

bprot

bsize

btran

btran[1:0]

ARM Memory

Controller

(including Decoder,

EBI and ARAM

Controller)

write_

master

address

APB

Peripherals

Bridge

blok[N-1:0]

Arbiter

(N masters)

agnt[N-1]

areq[N-1]

bwrite

agnt[i]

areq[i]

agnt

areq

Master

mabe

bprot_(N-1)

bsize_(N-1)

btran_(N-1)

BusEnable_(N-1)

ba_(N-1)

bwrite_(N-1)

bwrite

bsize

bprot

blok

bwrite

btran

BusEnable

agnt[N-1]agnt[i]

bsizeout

bprotout

baout

bwriteout

btranout

Master

Signals

Manager

not used in

this configuration

bprot_(i)

bsize_(i)

btran_(i)

BusEnable_(i)

ba_(i)

bwrite_(i)

bsize

agnt[N-1]

ARM7TDMI

Core and Wrapper

areq[N-1]

Arbiter

1284D–03/01

Functional

Description

The configuration described below is an example in which the arbiter manages six masters.

The waveforms which follow use the same configuration.

The arbitration scheme of this implementation is a simple priority encoded scheme where the

highest priority master requesting the ASB is granted.

Note: The priority order is defined differently during reset.

Priority In operational mode (reset inactive), the priority order is defined Table 2 from the highest prior-

ity to the lowest priority. If no request is present, the default master is granted and is in charge

of driving BTRAN to a valid value.

Note: During reset (active low), only the default master can be granted control of the bus. Therefore,

whatever the value of areq, agnt[5:0] is 000001.

Note: U takes the place of 0 or 1.

Table 2. Priority Level

Priority

Level Connection

Example

of Master

1 areq[0] and agnt[0] Default master

2 areq[1] and agnt[1] Debug

3 areq[2] and agnt[2] DMA

4 areq[3] and agnt[3] PDC

5 areq[4] and agnt[4] Coprocessor core

6 areq[5] and agnt[5] ARM® Core

Table 3. Arbitration Examples

Request Granted Response

areq[5:0] = UUUUU1 agnt [5:0] = 000001

areq[5:0] = UUUU10 agnt [5:0] = 000010

areq[5:0] = UUU100 agnt [5:0] = 000100

areq[5:0] = UU1000 agnt [5:0] = 001000

areq[5:0] = U10000 agnt [5:0] = 010000

areq[5:0] = 100000 agnt [5:0] = 100000

areq[5:0] = 000000 agnt [5:0] = 000001

Therefore:

areq[5:0] = 000101 agnt [5:0] = 000001

areq[5:0] = 011101 agnt [5:0] = 000001

areq[5:0] = 111110 agnt [5:0] = 000010

6Arbiter

1284D–03/01

Timing

Diagrams

The timing diagrams take into account the priority order described in Table 2.

During System Reset

and at the End of

System Reset

The master which has the lowest priority is always requesting the bus (typically the ARM

core).

Figure 4.

During system reset, Master[0](default master) is granted the bus. agnt is negative-edge

triggered.

nclock

nreset_f

100000

blok[5:0]

areq[5:0]

000001agnt[5:0] 100000

Inputs

Outputs

000000

Arbiter

1284D–03/01

Figure 5. Master [5] and Master [3] Requesting the Bus, Master [3] Granted After the End of Reset

Figure 6. Master Change [5] to [3]

nclock

nreset_f

101000

blok[5:0]

areq[5:0]

000001agnt[5:0] 001000

Inputs

Outputs

000000

nclock

nreset_f

100000areq[5:0]

000001agnt[5:0] 100000

Inputs

Outputs

111000

001000

blok[5:0] 000000

8Arbiter

1284D–03/01

Normal Operating

Mode

Figure 7. Master Change Between the Masters [5] and [4]: [5], [4], [5], [4], [5], [4]

Figure 8. Master Change Between the Masters [5] and [3]: [5], [3], [5], [3], [5], [3]

nclock

nreset_f

100000

blok[5:0]

areq[5:0]

agnt[5:0]

Inputs

Outputs

110000 100000 010000

010000 100000100000

100000

010000 010000

010000

000000

nclock

Inputs

nreset_f

100000

blok[5:0]

areq[5:0]

agnt[5:0]

Outputs

111000 100000 100000

100000

001000

001000 100000001000

001000

000000

001000

Arbiter

1284D–03/01

Figure 9. Master Change Between the Masters [4] and [2]: [4], [2], [4], [2], [4], [2]

Figure 10. Master Change Between the Masters [3] and [2]: [3], [2], [3], [2], [3]

nclock

nreset_f

110000

010000

blok[5:0]

areq[5:0]

agnt[5:0]

Inputs

Outputs

111100 010000 010000

010000

000100

000100 010000000100

000100

000000

000100

nclock

nreset_f

111000

blok[5:0]

areq[5:0]

agnt[5:0]

Inputs

Outputs

111100 001000 000100

001000 000100000100

001000

000000

001000

10 Arbiter

1284D–03/01

Figure 11. Master Changes with All Masters

Figure 12. Timing Data

nclock

nreset_f

100000

blok[5:0]

areq[5:0]

agnt[5:0]

Inputs

Outputs

000001001000

000011

110000

010000 000010010000

101000

110000 111000 000010

100000

000001

000000

nclock

nreset_f

blok[5:0]

areq[5:0]

agnt[5:0] 010000

Inputs

Outputs

100000

101000 100000 010000

000001 001000

tSU_AREQ tHOLD_AREQ

tHOLD_BLOK tSU_BLOK

tPD_AGNT

100000 000000000000

tPD_AGNT tPD_AGNT

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

Atmel Headquarters Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL (408) 441-0311

FAX (408) 487-2600

Europe

Atmel SarL

Route des Arsenaux 41

Casa Postale 80

CH-1705 Fribourg

Switzerland

TEL (41) 26-426-5555

FAX (41) 26-426-5500

Asia

Atmel Asia, Ltd.

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

Japan

Atmel Japan K.K.

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Atmel Colorado Springs

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL (719) 576-3300

FAX (719) 540-1759

Atmel Rousset

Zone Industrielle

13106 Rousset Cedex

France

TEL (33) 4-4253-6000

FAX (33) 4-4253-6001

Atmel Smart Card ICs

Scottish Enterprise Technology Park

East Kilbride, Scotland G75 0QR

TEL (44) 1355-357-000

FAX (44) 1355-242-743

Atmel Grenoble

Avenue de Rochepleine

BP 123

38521 Saint-Egreve Cedex

France

TEL (33) 4-7658-3000

FAX (33) 4-7658-3480

Fax-on-Demand

North America:

1-(800) 292-8635

International:

1-(408) 441-0732

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

BBS

1-(408) 436-4309

Printed on recycled paper.

1284D–03/01/xM

AMBA and ARM7TDMI are trademarks of ARM Ltd.

Terms and product names in this document may be trademarks of others.