Enpirion® Power Datasheet
EN6360QI 8A PowerSoC
Highly I nt egr ated Synchr onous
DC-DC Buck wit h I nt egr at ed Inductor
Description
The EN6360QI is a Power System on a Chip
(PowerSoC) DC to DC converter with an integrated
inductor, PWM controller, MOSFETs and
compensation to pr ovide the smallest solution size in
an 8x11x3mm 68 pin QFN module. It offers high
efficiency, excellent line and load regulation over
temperature and up to the full 8A load range. The
EN6360QI is specifically designed to meet the
precise voltage and fast transient requirements of
high-perfor m ance, low-pow er processor , DSP, FPGA,
memory boards and system level applications in
distributed power architecture. The EN6360QI
features switching frequency synchronization with an
external clock or other EN6360QIs for parallel
operation. Other features include precision enable
threshold, pre-bias monotonic start-up, and
programmable soft-start. The device’s advanced
circuit techniques, ultra high switching frequen cy, and
proprietary integrated inductor technology deliver
high-quality, ultra compact, non-isolated DC-DC
conversion.
The Altera Enpirion integrated inductor solution
significantly helps to reduce noise. The complete
power converter solution enhances productivity by
offering greatly simplified board design, layout and
manufacturing requirements. All Altera Enpirion
products are RoHS compliant and lead-free
manufactur ing environment compatible.
Features
• H i gh Efficiency (Up to 96% )
• Ex cellent Ripple and E M I P erform ance
• U p to 8A Continuous Operatin g Curre nt
• I nput V oltage R ange (2.5V to 6.6V )
• Frequency S ynchro niz ati on (Clock or P rim ary)
• 1.5% VOUT Accuracy (Over Load and Temperature)
• Optimized Total S olution Siz e (190mm2)
• Precision E nable Thresho ld for Sequen cing
• Program m able S oft-Start
• M aster/S lave Configurat ion for Paralle l Opera tion
• Therm al S hutdown, Over-Curr en t, S hort Circuit,
and Under-V oltage P rotection
• RoHS Compliant, MSL Level 3, 260°C Reflow
Applications
• Point of Load Regulati on for Low-Power, ASICs
Multi-Core and Communication Processors, DSPs,
FPGAs and Distributed P ow er A rchitectures
• Blade Servers, RAI D Storage and LAN/S AN
Adapter Cards, Wireless Base Stations, Industrial
Automation, Test and Measurement, Embedded
Computing, and Printers
• High Efficiency 12V Intermediate Bus Architectures
• Beat Frequency/N oi se Sensitive Appli cat ions
V
OUT
V
IN
2x
22µF
1206
VOUT
ENABLE
AGND
SS
PVIN
AVIN
PGND PGND
EN6360QI
15nF
VFB
R
A
R
B
R
1
C
A
FQADJ
2x
47µF
1206
R
FQADJ
Figure 1. S i m pl i fied Appl i cat i ons Circ ui t
Figure 2. Highest Eff icie ncy in Sm allest S olution Size
0
10
20
30
40
50
60
70
80
90
100
012 3 4 5 6 7 8
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
VOUT = 1.2V
CONDITIONS
V
IN
= 5.0V
Actual Solution Size
190mm
2
www.altera.com/enpirion
06489 March 24, 2015 Rev G
EN6360QI
Ordering Information
Part Number
Package Markings
Te m p Ra ting (°C)
Package Description
EN6360QI
EN6360QI
-40 to +85
68-pin (8mm x 11mm x 3mm) QFN T&R
EVB-EN6360QI
EN6360QI
QF N E valuati on B oard
Pac king and Ma rkin g Inf o rm ation: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Pin Assignments (Top View)
NC
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2
3
4
5
6
7
8
9
VOUT
VOUT
NC
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
NC
NC(SW)
NC(SW)
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
VDDB
NC
BGND
NC
S_IN
NC
NC
NC
NC
NC
NC(SW)
NC(SW)
FQADJ
EN_PB
NC
VSENSE
SS
EAOUT
VFB
M/S
AGND
AVIN
ENABLE
POK
S_OUT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
48
47
46
45
44
43
42
41
40
39
38
37
36
35
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
69
PGND
KEEP OUT
KEEP OUT
KEEP OUT
Figure 3: P i n O ut Di agram (Top V i ew)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they m ust be soldered to the P CB . F ai l ure t o foll ow t hi s gui del i ne m ay resul t i n part m al func ti on or dam age.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to the P CB. Refer t o F i gure 11 for detai l s.
NOTE C : Whi t e ‘ dot’ on top left i s pi n 1 i ndi cator on top of t he devi ce package.
Pin Description
PIN
NAME
FUNCTION
1-15, 25,
44-45,
59, 64-68
NC
NO CONNECT: T hese pins must be soldered to PCB but not electr ically connect ed to each
other or to any external signal, voltage, or ground. T hese pins may be conne ct ed internall y.
Failure to follow this guideline may result in device damage.
16-24 VOUT
Regulated converter output. Connect to the load and place output f ilter capacitor (s) between
these pins and PGND pins 28 to 31.
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06489 March 24, 2015 Rev G
EN6360QI
PIN
NAME
FUNCTION
26-27,
62-63 NC(SW)
NO CONN ECT : T hese pins are internally connected to the common swit chi ng node of the
internal MOSFET s. T hey must be soldered to PCB but not be electrically con nected to any
external signal, ground, or voltage. Failure to f ollow this guideli ne may result in device damage.
28-34 PGND
Input and output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. Ref er to VOUT, PVIN desc riptions and Layout Recomm endation for
more details.
35-43 PVIN
I nput power supply. Connect to input power supply and place input f ilter capacitor( s) between
these pins and PGND pins 32 to 34.
46 VDDB
I nternal regulated voltage used f or the internal control circuitry. D ecoupl e with an optional
0.1µF capacitor to BGND f or improved ef f iciency. T his pin may be left floating if board space is
limited.
47
BGND
Ground f or VDDB. Ref er to pin 46 description.
48 S_IN
Digital input. A high level on the M/S pin will make this EN6360QI a Slave and the S_IN will
accept the S_OUT signal f rom another EN6360QI for parallel operation. A low level on the M/S
pin will make this device a Master and the swit chi ng f requency will be phase locked to an
external clock. Leave this pin floating if it is not used.
49 S_OUT
Digital output. A low level on the M/S pin will make th is EN 6360QI a Master and the internal
switching PWM signal is output on this pin. This output signal is connect ed to the S_IN pin of
another EN6360QI device for parallel operation. Leave this pin floating if it is not used.
50 POK
POK is a logic level high when VOUT is w ithin -10% to +20% of the programmed outp ut
voltage (0.9VOUT_NOM ≤ VOUT ≤ 1.2VOUT_NOM). T his pin has an internal pull-up resistor to AVIN
with a nominal value of 94kΩ.
51 ENABLE
Device enable pin. A high level or floating this pin enables the device while a low level disables
the device. A voltage ramp fr om another power converter may be applied for pr ecision enable.
Ref er to Power U p Sequencing
52 AVIN
Analog input voltage for the control circuits. Connect this pin to the input power supply (PV IN)
at a quiet point. Can also be connected to an auxi liary supply w ithin a voltage range that is
sequencing.
53 AGND
The quiet ground f or the control circuits. Connect to the ground plane with a via right next to th e
pin.
54 M/S
Ternary (three states) input pin. Floati ng this pin disable s parallel operat ion. A low level
configures the device as Master and a high level conf igures the device as a Slave. A R EXT
resistor is recomm ended to pulli ng M/S high. Ref er to T ernary Pin descri ption in the Funct ional
Description section for REXT values. Also refer to S_IN and S_OUT pin descriptions.
55 VFB
T his is the external feedback input pin. A resist or divider connects f rom the output to AG ND.
The m i d-point of the resistor divider is connected to VFB . A feed-f orward capacitor (CA) and
resistor (R1) are required parallel to the upper feedback resistor (RA). T he output voltage
regulation is based on the VFB node voltage equal to 0.600V. For Sl ave devices, leave VFB
floating.
56
EAOUT
Error amplifier output. Allows for customi zat ion of the control loop. May be left floating.
57 SS
A soft-start capacito r is connect ed between this pin and AGND. T he value of the capacitor
controls the soft-start int erval. Ref er to Soft-Sta rt i n the Functional Descripti on for more details.
58 VSENSE
T his pin senses output voltage when the device is in pre-bias (or back-feed) mode. Connect
VSENSE to VOU T when EN_PB is high or f loating. Leave floating when EN_PB is low.
60 FQADJ
Frequency adjust pin. T his pin must have a resistor to AGND w hich s ets the free r unning
f requency of the internal oscillator.
61 EN_PB
Enable pre-bias input. When thi s pin is pulled high, the device will support monotonic start-up
under a pre-biased load. VSENSE must be tied to VOUT f or EN_PB to function. T his pin is
pulled high internally. Enable pre-bias f eature is not available for par allel operations.
69 PGND
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-
sinking purposes. Ref er to Layout Recom mendation section.
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EN6360QI
Absolute Maximum Ratings
CAUTION: Absolute M axi mum ratings are stress rati ngs only. Functi onal operat i on beyond the recom m ended operati ng
conditions is not implied. Stress beyond the absolute m axim um rati ngs m ay i m pai r device l i fe. E xpos ure to absol ute
m axi m um rat ed conditi ons for ex t ended peri ods m ay affect devi c e rel i abi l i t y.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Voltages on : PVI N , AVIN , VO U T
-0.3
7.0
V
Voltages on: EN, PO K, M/S
-0.3
V
IN
+0.3
V
Voltages on: VFB, EXTREF , EA O UT, SS, S_ IN , S _ OUT, FQ ADJ
-0.3
2.5
V
Storage T emperature Range
T
STG
-65
150
°C
Maximum Operating Junc tion T emperature
T
J-ABS Max
150
°C
Ref low T emp, 10 Sec, MSL3 JEDEC J -STD-020A
260
°C
ESD Rating (based on Human Body Model)
2000
V
ESD Rating (based on CDM)
500
V
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Voltage Range
V
IN
2.5
6.6
V
Output Voltage Range (Note 1)
V
OUT
0.60
V
IN
– V
DO
V
Output Current
I
OUT
8
A
Operating Ambient Temperature
T
A
-40
+85
°C
Operating Junction T emperature
T
J
-40
+125
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
T hermal Resistance: Junction to Ambie nt (0 LFM) (Note 2)
θJA
15
°C/W
T hermal Resistance: Junction to Case (0 LFM)
θJC
1.0
°C/W
T hermal Shutdown
T
SD
150
°C
T hermal Shutdown Hysteresi s
T
SDH
20
°C
Note 1: VDO (dropout voltage) is defined as (ILOAD x Dropout Resistance). Please ref er to E l ectri cal Charac teri sti cs Tabl e.
Note 2: Based on 2oz. external copper layers and proper thermal design i n l i ne with EIJ/JE DE C JES D51-7 standard for
high therm al conducti vity boards.
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06489 March 24, 2015 Rev G
EN6360QI
Electrical Characteristics
NOTE: VIN=6.6V, Mi nim um and Maxim um values are over operating ambient tem perature range unless otherwise not ed.
Typical values are at TA = 25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating I nput
Voltage VIN 2.5 6.6 V
VFB Pin Voltage VVFB
Internal Voltage Reference at:
VIN = 5V, ILOAD = 0, TA = 25°C 0.594 0.600 0.606 V
VFB Pin Voltage (Loa d
and T emperature) VVFB
0A ≤ I
LOAD
≤ 8A
Starting Date Code: X501 or greater 0.591 0.600 .609 V
VFB Pin Voltage
(Line, Load and
Temperature) VVFB 2.5V ≤ VIN ≤ 6.6V
0A ≤ ILOAD ≤ 8A 0.588 0.600 0.612 V
VFB Pin Input Leakage
Current IVFB
VFB Pin Input Leakage Current
(Note 4) -10 10 nA
Shut-Dow n Supply
Current IS
Power Supply Current with
ENABLE=0 1.5 mA
Under Voltage Lock-
out – VIN Rising VUVLOR
Voltage Above Which UVLO is Not
Asserted 2.2 V
Under Voltage Lock-
out – VIN Falling VUVLOF
Voltage Below Which U VLO is
Asserted 2.1 V
Drop Out Voltage
VDO VINMIN – VOUT at Full Load 400 800 mV
Drop Out Resistance
R
DO
I nput to Output Resistance
50
100
mΩ
Continuous Output
Current IOUT_SRC 0 8 A
Over Current T rip
Level IOCP Sourcing Current 16 A
Switching Frequency
F
SW
R
FADJ
= 4.42 kΩ, V
IN
= 5V
0.9
1.2
1.5
MHz
External SYNC Clock
Frequency Lock
Range FPLL_LOCK SYNC Clock Input Frequency
Range 0.9*Fsw Fsw 1.1*Fsw MHz
S_IN C lock Amplitude
– Low VS_IN_LO SYNC Clock Logic Low 0 0.8 V
S_IN C lock Amplitude
– High VS_IN_HI SYNC Clock Logic High 1.8 2.5 V
S_ IN Cl o ck D uty Cycle
(PLL) DCS_INPLL M/S Pin Float or Low 20 80 %
S_ IN Cl o ck D uty Cycle
(PWM) DCS_INPWM M/S Pin High 10 90 %
Pre-Bias Level VPB
Allowable Pre-bias as a Fracti on of
Programmed Output Voltage f or
Monotonic start up. Minim um Pre-
bias Voltage = 300mV. 20 75 %
Non-Monotonicity VPB_NM
Allowable Non-monotonicity Under
Pre-bias Startup 100 mV
VOUT Range f or POK =
High
Range of Output Voltage as a
Fraction of Programmed Value
When POK is Asserted. (Note 3) 90 120 %
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06489 March 24, 2015 Rev G
EN6360QI
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POK Deglitch Delay
Falling Edge Deglitch Delay After
Output Cr ossing 90% level.
FSW=1.2 MHz 213 µs
V
POK
Logic Low level
With 4mA Current Sink into P
OK
Pin
0.4
V
V
POK
Logic high level
V
IN
V
POK Internal pull-up
resistor 94 kΩ
Curr ent Balance ∆IOUT
With 2 to 4 Converters in Parallel,
the Difference Between Nominal
and Actual Current Levels.
∆VIN<50mV; RTRACE< 10 mΩ,
Iload= # Convert er * IMAX
+/-10 %
VOUT Rise T ime
Accuracy ∆TRISE
(Not e 4)
t
RISE
[ms] = C
SS
[nF] x 0.065;
10nF ≤ CSS ≤ 30nF;
(Note 5 and Note 6) -25 +25 %
ENABLE Logic High
V
ENABLE_HIGH
2.5V ≤ V
IN
≤ 6.6V;
1.2
V
IN
V
ENABLE Logic Low
V
ENABLE_LOW
0
0.8
V
ENABLE Pin Curr ent
I
EN
VIN = 6.6V
50
µA
M/S T ernary Pin Logic
Low VT-LOW Tie M/S Pin to GND 0 0.7 V
M/S T ernary Pin Logic
Float VT-FLOAT M/S Pin is Open 1.1 1.4 V
M/S T ernary Pin Logic
Hi (Note 7) VT-HIGH
Pull Up to VI N through an external
resistor REXT . Ref er to Figure 7. 1.8 V
T ernary Pin Input
Current ITERN
2.5V ≤ V
IN
≤ 4V, R
EXT
= 15k
Ω
4V < VIN ≤ 6.6V, REXT = 51kΩ
117
88 µA
Binary Pin Logic Low
Threshold VB-LOW EN ABL E, S_ I N 0.8 V
Binary Pin Logic H igh
Threshold VB-HIGH EN ABL E, S_ I N 1.8 V
S_OUT Low Level
V
S_OUT_LOW
0.4
V
S_OUT H igh Level
V
S_OUT_HIGH
2.0
V
Note 3: POK threshol d when VOUT is rising is nominall y 92%. T his threshold is 90% when VO UT is falling. After crossing
the 90% level, there is a 256 clock cyc le (~21 3µ s at 1.2 MHz) delay bef ore POK is de-ass erted. The 90% and 92% l evels
are nomi nal values. E xpec t these threshol ds to vary by ± 3% .
Note 4: Param eter not producti on tested but i s guaranteed by design.
No te 5: Ri se ti m e calculation begi ns when AVIN > VUVLO and ENABLE = HIGH.
No te 6: VOUT Rise Ti m e A cc uracy does not i ncl ude soft -s tart capac i tor tolerance..
Note 7: M/S pin is ternary. T ernary pins have three logic levels: hi gh, float, and l ow. This pi n is m eant to be strapped t o
VIN through an external resistor, strapped to G ND, or l eft floati ng. The s tate cannot be changed whi le the devi c e i s on.
www.altera.com/enpirion, P age 6
06489 March 24, 2015 Rev G
EN6360QI
Typical Performance Curves
0
10
20
30
40
50
60
70
80
90
100
012345678
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Effic ie ncy vs. Output Current
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 3.3V
0
10
20
30
40
50
60
70
80
90
100
01234567 8
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Effic ie ncy vs. Output Current
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 5.0V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
012345678
O UTPUT VOLTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 1.8V
CONDITIONS
V
IN
= 3.3V
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
012345678
O UTPUT VOLTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 1.0V
CONDITIONS
V
IN
= 3.3V
3.280
3.285
3.290
3.295
3.300
3.305
3.310
3.315
3.320
012345678
O UTPUT VOLTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 3.3V
CONDITIONS
V
IN
= 5.0V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
012345678
O UTPUT VOLTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 1.8V
CONDITIONS
V
IN
= 5.0V
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06489 March 24, 2015 Rev G
EN6360QI
Typical Performance Curves (Continued)
0.980
0.985
0.990
0.995
1.000
1.005
1.010
1.015
1.020
01234567 8
O UTPUT VOLTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VOUT = 1.0V
CONDITIONS
V
IN
= 5.0V
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.4 33.6 4.2 4.8 5.4 66.6
O UTPUT VOLTAGE (V)
INPUT VOL T AG E (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = 0A
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.4 33.6 4.2 4.8 5.4 66.6
O UTPUT VOLTAGE (V)
INPUT VOL T AG E (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = 4A
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
2.4 33.6 4.2 4.8 5.4 66.6
O UTPUT VOLTAGE (V)
INPUT VOL T AG E (V)
Output Voltage vs. Input Voltage
CONDITIONS
Load = 8A
1.794
1.795
1.796
1.797
1.798
1.799
1.800
1.801
1.802
-40 -15 10 35 60 85
O UTPUT VOLTAG E (V)
AM BIENT T EMPERAT URE ( C)
Output Voltage vs. Tem pe rature
LOAD = 0A
LOAD = 2A
LOAD = 4A
LOAD = 6A
LOAD = 8A
CONDITIONS
V
IN
= 6.6V
V
OUT_NOM
= 1. 8V
1.794
1.795
1.796
1.797
1.798
1.799
1.800
1.801
1.802
-40 -15 10 35 60 85
O UTPUT VOLTAG E (V)
AM BIENT T EM P ERATURE ( C)
Output Voltage vs . Tem perature
LOAD = 0A
LOAD = 2A
LOAD = 4A
LOAD = 6A
LOAD = 8A
CONDITIONS
V
IN
= 5V
V
OUT_NOM
= 1. 8V
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06489 March 24, 2015 Rev G
EN6360QI
Typical Performance Curves (Continued)
1.794
1.795
1.796
1.797
1.798
1.799
1.800
1.801
1.802
-40 -15 10 35 60 85
O UTPUT VOLTAG E (V)
AM BIENT T EMPERAT URE ( C)
Output Voltage vs. Tem pe rature
LOAD = 0A
LOAD = 2A
LOAD = 4A
LOAD = 6A
LOAD = 8A
CONDITIONS
V
IN
= 3.6V
V
OUT_NOM
= 1. 8V
1.794
1.795
1.796
1.797
1.798
1.799
1.800
1.801
1.802
-40 -15 10 35 60 85
O UTPUT VOLTAG E (V)
AM BIENT T EMPERAT URE ( C)
Output Voltage vs. Tem pe rature
LOAD = 0A
LOAD = 2A
LOAD = 4A
LOAD = 6A
LOAD = 8A
CONDITIONS
V
IN
= 2.5V
V
OUT_NOM
= 1. 8V
0
1
2
3
4
5
6
7
8
9
10
-40 -15 10 35 60 85
G UA RANTEED O UTPUT CURRENT (A)
AM BIENT T EMPERAT URE( C)
No Thermal Derating
Conditions
V
IN
= 5.0V
V
OUT
= 3. 3V
CONDITIONS
V
IN
= 5.0V
V
OUT
= 3. 3V
0
1
2
3
4
5
6
7
8
9
10
-40 -15 10 35 60 85
G UA RANTEED O UTPUT CURRENT (A)
AM BIENT T EMPERAT URE( C)
No Thermal Derating
Conditions
V
IN
= 5.0V
V
OUT
= 3. 3V
CONDITIONS
V
IN
= 5.0V
V
OUT
= 1. 0V
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
30 300
LEVEL (dBµ V/m)
FREQ UENCY (MHz)
EMI Perfor mance (Hor izontal Scan)
CONDITIONS
VIN = 5.0V
VOUT_NOM = 1.5V
LOAD = 0 .2 Ω
CISPR 22 Class B 3m
10.0
20.0
30.0
40.0
50.0
60.0
70.0
80.0
90.0
100.0
30 300
LEVEL (dBµ V/m)
FREQ UENCY (MHz)
EMI Performance (Vertical Scan)
CONDITIONS
V
IN
= 5.0V
V
OUT_NOM
= 1. 5V
LOAD = 0 .2 Ω
CISPR 22 Class B 3m
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EN6360QI
Typical Parallel Performance Curves
0
10
20
30
40
50
60
70
80
90
100
0246810 12 14 16
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Parallel Eff iciency
vs. Output Current
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 3.3V
2x EN6360QI
0
10
20
30
40
50
60
70
80
90
100
0246810 12 14 16
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Parallel Eff iciency
vs. Output Current
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 5.0V
2x EN6360QI
-5
-4
-3
-2
-1
0
1
2
3
4
5
2 4 6 8 10 12 14 16
CURRENT MIS-MATCH (%)
OUT PUT CURRENT (A)
Parallel Cur rent Share Mis-Match
Mis-match (%) = (I_Master -I_Slave ) / I_Average x 100
CONDITIONS
EN6360QI
VIN = 5V
VOUT = 3.3V
0
1
2
3
4
5
6
7
8
9
10
246810 12 14 16
INDIVI DUAL OUT PUT CURRENT (A)
TOTAL OUTPUT CURRENT (A)
Par allel C ur ren t Shar e Br eakdown
Master Device
Slave Device
CONDITIONS
EN6360QI
V
IN
= 5V
V
OUT
= 3. 3V
3.2
3.22
3.24
3.26
3.28
3.3
3.32
3.34
3.36
3.38
3.4
0246810 12 14 16
PARALLEL O UTPUT VOLTAG E (V)
OUT PUT CURRENT (A)
Parallel O utput Voltage
vs. Output Current
VOUT = 3.3V
CONDITIONS
V
IN
= 5.0V
2x EN6360QI
0.9
0.92
0.94
0.96
0.98
1
1.02
1.04
1.06
1.08
1.1
0246810 12 14 16
PARALLEL O UTPUT VOLTAG E (V)
OUT PUT CURRENT (A)
Parallel O utput Voltage
vs. Output Current
VOUT = 1.0V
CONDITIONS
V
IN
= 3.3V
2x EN6360QI
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06489 March 24, 2015 Rev G
EN6360QI
Typical Performance Characteristics
VOUT
(A C C ouple d)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 5V
VOUT = 1V
IOUT = 8A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
VOUT
(A C C ouple d)
Output Ripple at 500MHz Ba ndwidth
CONDITIONS
VIN = 5V
VOUT = 1V
IOUT = 8A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
VOUT
(A C C ouple d)
Output Ripple at 20MHz Bandwidth
CONDITIONS
VIN = 5V
VO UT = 2.4V
IOUT = 8A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
VOUT
(A C C ouple d)
Output Ripple at 500MHz Ba ndwidth
CONDITIONS
VIN = 5V
VO UT = 2.4V
IOUT = 8A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
ENABLE
Enable Power Up/Down
CONDITIONS
VIN = 5V
VO UT = 1.0V
IOUT = 8A
Css = 15nF
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
VOUT
ENABLE
Enable Power Up/Down
CONDITIONS
VIN = 5V
VO UT = 2.4V
IOUT = 8A
Css = 15nF
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
VOUT
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EN6360QI
Typical Performance Characteristics (Continued)
ENABLE
Enable/Disable with POK
CONDITIONS
VIN = 5V, VOUT = 1.0V
LOAD = 5A, Css= 15nF
VOUT
POK
LOAD
VOUT
(A C C ouple d)
Load Transient from 0 to 8A
CONDITIONS
VIN = 6.2V
VO UT = 1.5V
CIN = 2 x 22µF (1206)
CO U T = 2 x 47µF (1206)
LOAD
Parallel Op eration SW Wavef orms
CONDITIONS
VIN = 5V
VOUT = 1.8V
LOAD = 18A
COMBINED LOAD(18A)
MASTER VSW
SLAVE 2 VSW
SLAVE 1 VSW
Parallel Op eration Current Sharing
CONDITIONS
VIN = 5V
VOUT = 1.8V
LOAD = 18A
SLAVE 1 LOAD = 6A
SLAVE 2 LOAD = 6A
TOTAL LOAD = 18A
MASTER LOAD = 6A
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EN6360QI
Functional Block Diagram
Soft Start
Power
Good
Logic
Bandgap
Reference
MUX
Compensation
Network
Thermal Limit
UVLO
Current Limit P-Drive
N-Drive
PLL/Sawtooth
Generator
FQADJ
ENABLE
SS
AGND
POK
VSENSE
VFB
PGND
S_OUT
NC(SW)
PVIN
To PLL
Error
Amp
PWM
Comp
(+)
(-)
(-)
(+)
Digital I/O
S_IN
M/S VDDB
VOUT
AVIN
AVIN
EN_PB
Reference
Voltage
Selector
EAOUT
EAOUT
MUX
AVIN
AVIN
BGND
Eff
94k
24k
24k
Figure 4: F uncti onal B l ock Di agram
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EN6360QI
Functional Description
The EN6360QI is a synchronous, programmable
buck power supply with integrated power MOSF ET
switches and integrated inductor. The switching
supply uses voltage mode control and a low noise
PWM topology. This provides superior impedance
matching to ICs processed in sub 90nm process
technologies. The nominal input voltage range is
2.5 - 6.6 volts. The output voltage is programmed
using an external resistor divider network. The
feedback control loop incorporates a type IV
voltage m ode control design. Type I V voltage m ode
control maximizes control loop bandwidth and
maintains excellent phase margin to improve
transient perform ance. The EN6360QI is designed
to support up to 8A continuous output current
operation. The operating switching frequency is
between 0.9MHz and 1.5MHz and enables the use
of small-size input and output capacitor s.
The power supply has the following features:
• Precision Enable Threshold
• Soft-Start
• Pre-bias Start-Up
• Resistor Programmable Switching Frequency
• Phase-Lock Frequency Synchronization
• Parallel Operation
• Power OK
• Over-Current/Short Circuit Protection
• Thermal Shutdow n with Hysteresis
• Under-Voltage Lockout
Pre cision Enable
The ENABLE threshold is a precision analog
voltage rather than a digital logic threshold. A
precision voltage reference and a comparator
circuit are kept powered up even when ENABLE is
de-asserted. The narrow voltage gap between
ENABLE Logic Low and ENABLE Logic High
allows the device to turn on at a precise enable
voltage level. With the enable thresho l d pinpo inted,
a proper choice of soft-start capacitor helps to
accurately sequence multiple power supplies in a
system as desired. There is an ENABLE lockout
time of 2ms that prevents the device from re-
enabling immediately after it is disabled.
Soft-Start
The SS pin in conjunction with a small external
capacitor between this pin and AGND provides a
soft-start function to limit in-rush current during
device power-up. When the part is ini tially powered
up, the output voltage is gradually ramped to its
final value. The gradual outpu t ram p is achieved by
increasing the reference voltage to the error
amplifier. A constant current flowing into the soft-
start capacitor provides the refer en ce voltage ramp .
When the voltage on the soft-start capacitor
reaches 0.60V, the output has reached its
program m ed voltage. Once the output voltage has
reached nom inal voltage the soft-star t capacit or wil l
continue to charge to 1.5V (Typical). The output
rise time can be controlled by the choice of soft-
start capacitor value.
The rise time is defined as the time from when the
ENABLE signal crosses the threshold and the input
voltage crosses the upper UVLO threshold to the
time when the output voltage reaches 95% of the
program m ed value. The rise time (tRISE) is given by
the following equation:
tRISE [ms] = Css [nF] x 0.065
The rise time (tRISE) is in milliseconds and the soft-
start capacitor (CSS) is in nano-Farads. The soft-
start capacitor should be between 10n F and 100 n F .
Pre-Bias Start-up
The EN6360QI supports startup into a pre-biased
load. A proprietary circuit ensures the output
voltage rises up from the pre-bias value to the
program m ed output voltage . S tart-up is guara ntee d
to be monotonic for pre-bias voltages in the range
of 20% to 75% of the programmed output voltage
with a minimum pre-bias voltage of 300m V. Outside
of the 20% to 75% range, the output voltage rise
will not be monotonic. The Pre-Bias feature is
automatically engaged with an internal pull-up
resistor. For this feature to work properly, VIN must
be ramped up prior to ENABLE turning on the
device. T ie VSENSE to VOUT if Pr e-Bias is used.
Tie EN_PB to ground and leave VSENSE floating
to disable the Pre-Bias feature. Pre-Bias is
supported for external clock synchronization, but
not supported for par allel operations.
Resistor Programmable Frequency
The operation of the EN6360QI can be optimized
by a proper choice of the RFQADJ resistor. The
frequency can be tuned to optimize dynamic
performance and efficiency. Refer to Table 1 for
recommended RFQADJ values.
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06489 March 24, 2015 Rev G
EN6360QI
Ta bl e 1: Recom m ended RFQADJ (kΩ)
V
OUT
VIN
0.8V 1.2V 1.5V 1.8V 2.5V 3.3V
3.3V ±10%
3.57
3.57
4.99
5.49
5.49
NA
5.0V ±10%
3.57
3.57
4.99
5.49
5.49
4.99
6.0V ±10%
3.57
3.57
4.99
5.49
5.49
5.49
Phase-Lock Ope ration:
The EN6360QI can be phase-locked to an external
clock signal to synchronize its switching frequency.
The M /S pin can be left floating or pulled to ground
to allow the device to synchronize with an exter nal
clock signal using the S_IN pin. When a clock
signal is present at S_IN, an activity detector
recogniz es the presence of the clock signal and th e
internal oscillator phase locks to the ex ternal clock.
The ex ternal clock could be the system clock or the
output of another EN6360QI. The phase locked
clock is then output at S_OUT. Refer to Table 2 for
recommended clock frequencies.
Ta bl e 2: Recom m ended Cl oc k fsw (M Hz)±10%
V
OUT
VIN
0.8V 1.2V 1.5V 1.8V 2.5V 3.3V
3.3V ±10%
1.15
1.15
1.30
1.35
1.35
NA
5.0V ±10%
1.15
1.15
1.30
1.35
1.35
1.30
6.0V ±10%
1.15
1.15
1.30
1.35
1.35
1.35
Master / Slave (Parallel) Operation and
Fre que ncy Synchroniz ation
Multiple EN6360QI devices may be connected in a
Master/Slave configuration to handle larger load
currents. The device is placed in Master mode by
pulling the M/S pin low or in Slave mode by pulling
M /S pin high. W hen the M/S pin is in flo at st at e,
parallel operation is not possible. In Master
mode, a version of the internal switching PWM
signal is output on the S_OUT pin. This PWM
signal from the Master is fed to the Slave device at
its S_IN pin. The Slave device acts like an
extension of the power FETs in the Master and
inherits the PWM frequency and duty cycle. The
inductor in the Slave prevents crow-bar currents
from Master to Slave due to timing delays. The
Master device’s switching clock may be phase-
locked to an external clock source or another
EN6360QI to move the entire parallel operation
frequency away from sensitive frequencies. The
feedback network for the Slave device may be left
open. Additional Slave devices may be paralleled
together with the Master by connecting the S_OUT
of the M aster to the S_I N of all other Slave devices.
Refer to Figure 5 for details.
Careful attention is needed in the layout for parallel
operation. The VIN, VOUT and GND of the
paralleled devices should have low impedance
connections between each other. Maximize the
amount of copper used to connect these pins and
use as many vias as possible when using multiple
layers. Place the Master device between all other
Slaves and closest to the point of load.
EN6360QI
MASTER
EN6360QI
SLAVE1
S_OUT
S_IN
S_IN
VOUT
VOUT
VOUT
VIN
VIN
VIN
GND
GND
GND
VFB
VFB
VFB
Feedback &
Compensation
OPEN
OPEN
OPEN
VIN
VOUT
M/S
M/S
M/S
EN6360QI
SLAVE2
EN6360QI
SLAVE3
S_IN
VOUT
VIN
GND
VFB
M/S
R
EXT
R
EXT
R
EXT
Figure 5: M aster/S l ave P aral lel O perat i on Diagram
POK Operation
The POK signals that the output voltage is within
the specified range. The POK signal is asserted
high when the rising output voltage crosses 92%
(nominal) of the progr ammed output voltage. If the
output voltage falls outside the range of 90% to
120%, POK rem ains asserted for the de-glit c h time
(213µs at 1.2M Hz ). After the de-glit c h time, POK is
de-asserted. POK i s also de-asser ted if the output
voltage exceeds 120% of the programmed output
voltage.
Over Current Protection
The current limit function is achieved by sensing
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EN6360QI
the current flowing through a sense P-FET. When
the sensed current exceeds the curr ent limit, both
power FETs are turned off for the rest of the
switching cycle. If the over-current condition is
rem oved, the over-current pr otection circuit will re-
enable PWM operation. I f the over-cur ren t condit io n
persists, the circuit will continue to protect the load.
The OCP trip point is nominally set as specified in
the E lectrical Characteristics table. I n the event the
OCP circuit trips consistently in normal operation,
the device enters a hiccup mode. The device is
disabled for 27ms and r estarted with a normal soft-
start. This cycle can conti nue indefinite ly as long as
the over curr ent condition persists.
Therm al Overload Protection
Temperature sensing circuits in the controller will
disable operation when the junction temperature
exceeds approximately 150ºC. Once the junction
temperature drops by approx 20ºC, the converter
will re-start with a normal soft-start.
Input Unde r-Voltage Lock-Out
When the input voltage is below a required voltage
level (VUVHI) for normal operation, the converter
switching is inhibited. The lock-out threshold has
hysteresis to prevent chatt er. Th us w hen the devic e
is operating normally, the input voltage has to fall
below the lower threshold ( VUVLO) for the device to
stop switching.
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EN6360QI
Application Information
Output Voltage Programming a nd loop
Compensation
The EN6360QI output vol tage is progra m m ed usin g
a simple resistor divider network. A phase lead
capacitor plus a resistor are required for stabiliz ing
the loop. Figure 6 shows the required components
and the equations to calculate their values.
The EN6360QI output vol tage is determ ined by the
voltage presented at the VFB pin. This voltage is
set by way of a resistor divider between VOUT and
AGND with the midpoint going to VFB.
The EN6360QI uses a type IV compensation
network. Most of this network is integrated.
However, a phase lead capacitor and a resistor are
required in parallel with upper resistor of the
external feedback netw ork (Refer to Figure 6). Total
compensation is optimized for use with two 47μF
output capacitance and will result in a wide loop
bandwidth and excellent l oad transient perf orma n ce
for most applications. Additional capacitance may
be placed beyond the voltage sensin g point out sid e
the control loop. Voltage mode oper ation provides
high noise immunity at light load. Furthermore,
voltage m ode control provides superior im pedance
matching to ICs processed in sub 90nm
technologies.
In some cases modifications to the compensation
or output capacitance may be required to optimize
device performance such as transient response,
ripple, or hold-up tim e. The EN6360QI provides the
capability to modify the control loop response to
allow for customization for such applications. For
more information, contact Power Applications
support.
VOUT
VFB
R
A
C
A
R1
R
B
Fi gure 6: External Feedback/Compensation Network
The feedback and compensation network values
depend on the input voltage and output voltage.
Calcul ate the ex ternal feedback and com pensation
network values with the equations below.
RA [Ω] = 48,400 x VIN [V]
*Round RA up to closest standard value
RB[Ω] = (VFB x RA) / ( VOUT – VFB) [V]
VFB = 0.6V nom inal
*Round RB to closest standard value
CA [F] = 3.83 x 10-6 / RA [Ω]
*Round CA down to closest standard value
R1 = 15kΩ
The feedback resistor network should be sens ed at
the last output capacitor close to the device. Keep
the trace to VFB pin as short as possible.
Whenever possible, connect RB directly to the
AGND pin instead of goi ng through the GN D plane.
Input Capacitor Se le ction
The EN6360QI has been optim ized for use w ith two
1206 22µF input capacitors. Low ESR ceramic
capacitors are required with X5R or X7R dielectric
formulation. Y5V or equivalent dielectric
formulations must not be used as these lose
capacitance with frequency, temper atur e and bias
voltage.
In some applications, lower value ceramic
capacitors m ay be needed in parallel with the larg e r
capacitors in order to provide high frequency
decoupling. The capacitors shown in the table
below are typical input capacitors. Other capa citors
with similar characteristics may also be used.
Ta bl e 3: Recom m ended Input Capac i tors
Description
MFG
P/N
22µF, 10V, 20%
X5R, 1206
(2 capacitors needed)
Murata
GRM31CR61A226ME19L
Taiyo Yud e n
LMK316BJ226ML-T
Output Capac itor Selection
The EN6360QI has been optim ized for use w ith two
1206 47µF output capacitors. Low ESR, X5R or
X7R ceramic capacitors are recommended as the
primary choice. Y5V or equivalent dielectric
formulations must not be used as these lose
capacitance with frequency, temper atur e and bias
voltage. The capacitors shown in the
Recom m ended Output Capacito rs table are typical
output capacitors. Other capacitors with similar
characteristics may also be used. Additional bulk
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06489 March 24, 2015 Rev G
EN6360QI
capacitance from 100µF to 1000µF may be placed
beyond the voltage sensing point outside the
control loop. This additional capacitance should
have a minimum ESR of 6mΩ to ensure stable
operation. M ost tantalum capacitor s will have mor e
than 6mΩ of ESR and may be used without special
care. Adding distance in layout may help incr ease
the ESR between the feedback sense point and th e
bulk capacitors.
Ta bl e 4: Recom m ended Output Capaci tors
Description
MFG
P/N
47µF, 10V, 20%
X5R, 1206
(2 capacitors needed)
T aiyo Yuden LMK316BJ476ML-T
47µF, 6.3V, 20%
X5R, 1206
(2 capacitors needed)
Murata
GRM31CR60J476ME19L
T aiyo Yuden
JMK316BJ476ML-T
10µF, 6.3V, 10%
X7R, 0805
(Optional 1 capacitor in
paral lel wi th 2x47µF)
Murata
GRM21BR70J106KE76L
T aiyo Yuden JMK212B7106KG-T
Output ripple voltage is prim arily determ ine d by the
aggregate output capacitor impedance. Placing
multiple capacitors in parallel reduces the
impedance and hence will result in lower ripple
voltage.
nTotal ZZZZ 1
...
111
21
+++=
Ta bl e 5: Typi cal Rippl e Vol tages
Output Capaci tor
Configuration Typica l Output Ri ppl e (mV p-p)
2 x 47 µF
<10mV
† 20 MHz bandwidth limit measured on Evaluation Board
M/S - Ternary Pin
M/S is a ternary pin. T his pin can assume 3 states
– A low state (0V to 0.7V), a high state (1.8V to
VIN) and a float state (1.1V to 1.4V). Device
operation is controlled by the state of the pin. T he
pins m ay be pulled to ground or left floating w ithout
any special care. When pull ing high to VIN, a series
resistor is recommended. The resistor value may
be optimized to reduce the current drawn by the
pin. The resistance should not be too high as in th a t
case the pin m ay not recognize the high state. The
recommend resistance (REXT) value is given in the
following table.
Ta bl e 5: Recom m ended REXT Resistor
VIN (V) IMAX (µA) REXT (kΩ)
2.5 – 4.0
117
15
4.0 – 6.6
88
51
2.5V
To Gates
R
EXT
R1
134k
R2
134k
To V
IN
R3
319
D1
Vf ≈ 2V
Inside EN6360QI
AGND
M/S
Fi gure 7: S el ecti on of REXT to Connec t M /S pi n to V IN
Ta bl e 6: M /S (M aster/ Sl ave) Pi n States
M/S Pin
Function
Low
(0V t o 0.7V)
M/S pin is pulled to ground directly. T h is is
the Master mode. Switchi ng PWM phase
will lock onto S_IN external clock
if a signal
is available. S_OUT outputs a version of
the internal switching PW M signal.
Float
(1.1V to 1.4V)
M/S pin is left f loating. Parallel operation is
not feasible. Switchi ng PWM phase will
lock onto S_IN external clock if a signal is
available. S_OUT outputs a version of t he
internal switching P WM si gnal.
High
(>1.8V)
M/S pin is pulled to VIN with R
EXT
. Th is is
the Slave mode. T he S_IN signal of the
Slave should connect to the S _OUT of the
Master device. T his signal synchronizes
the switching fr equency and duty cyc le of
the Master to the Slave device.
Power-Up Sequencing
Dur ing power-up, ENABLE should not be asserted
before PVIN, and PVIN should not be asserted
before AVIN. Tying all three pins together meets
these requirements.
Technical Support
Contact Altera for additional support regarding the
use of this product (www.altera.com/support).
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06489 March 24, 2015 Rev G
EN6360QI
Thermal Considerations
Therm al consideratio ns are im porta nt power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for. The Altera
Enpirion PowerSoC helps alleviate some of those
concerns.
The Altera Enpirion EN6360QI DC-DC converter is
packaged in an 8x11x3mm 68-pin QFN package.
The QF N package is constructed with copper lead
frames that have exposed thermal pads. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The r ecommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protecti on circuit designed to turn off the device at
an approximate junction temperature value of
150°C.
The EN6360QI is guaranteed to support the full 8A
output current up to 85°C ambient temperature.
The following example and calculations illustrate
the thermal performance of the EN6360QI.
Example:
VIN = 5V
VOUT = 3.3V
IOUT = 8A
First calculate the output power.
POUT = 3.3V x 8A = 26.4W
Next, determine the input power based on the
efficiency (η) shown in Figure 8.
Fi gure 8: Efficiency vs. O ut put Current
For VIN = 5V, VOUT = 3.3V at 8A, η ≈ 94%
η = POUT / PIN = 94% = 0.94
PIN = POUT / η
PIN ≈ 26.4W / 0.94 ≈ 28.085W
The pow er dissipati on (PD) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
PD = PIN – POUT
≈ 28.085W – 26.4W ≈ 1.685W
With the pow er dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how m uch the tem perature will rise in the device for
every watt of power dissipation. The EN6360QI has
a θJA value of 15 ºC/W without airflow.
Determine the change in temperature (ΔT) based
on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 1.685W x 15°C/W = 25.28°C ≈ 25.3°C
The junction temperature (TJ) of the device is
approximately the ambient temperature (TA) plus
the change in temperature. We assume the initial
ambient temper ature to be 25° C.
TJ = TA + ΔT
TJ ≈ 25°C + 25.3°C ≈ 50.3°C
With 1.685W dissipated into the device, the TJ will
be 50.3°C.
The maximum operating junction temperature
(TJMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
m ax i m um am bient tem perature (TAMAX) allowed can
be calculated.
TAMAX = TJMAX – PD x θJA
≈ 125°C – 25.3°C ≈ 99.7°C
The ambient temperature can actually rise by
another 74.7°C, bringing it to 99.7°C before the
device will reach TJMAX. This indicates that the
EN6360QI can support the full 8A output current
range up to approximately 99.7°C ambient
temperature given the input and output voltage
conditions. This allows the EN6360QI to guarantee
full 8A output current capability at 85°C with room
for margin. Note that the efficiency will be slightly
lower at higher temperatures and this es timat e will
be slightly lower.
0
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40
50
60
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012345678
EFFI CIENCY (%)
OUT PUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
CONDITIONS
VIN = 5.0V
94%
www.altera.com/enpirion, P age 19
06489 March 24, 2015 Rev G
EN6360QI
Layout Recommendation
Fi gure 10: Top Lay out wi t h Cri t i cal Com ponents O nl y
(Top Vi ew). S ee F i gure 9 for corres pondi ng sc hem ati c.
This l ayout only shows the critical com ponents and
top layer traces for minimum footprint in single-
supply mode with ENABLE tied to AVIN. Alternate
circuit configurations & other low-power pins need
to be connected and routed according to custom er
application. Please see the Gerber files at
http://www.altera.com/enpirion for details on all
layers.
Recommendation 1: I nput and output filter
capacitors should be placed on the sam e side of
the P CB , and as close to the EN6360QI package
as possible. They should be connect ed to the
device with very short and wi de traces. Do not use
therm al reliefs or spokes when connecting the
capacitor pads to the respective nodes . The +V a n d
GND traces betw een the capacitors and the
EN6360QI should be as close to each other as
possible so that the gap between the two nodes is
m ini m ized, even under the capacitors.
Recommendation 2: The PGND connections for
the input and output capacitors on layer 1 need to
have a slit between them in order to pr ovide some
separation between input and output current loops.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
conti nuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 4: The therm al pad underneath
the component must be connected to the system
ground plane through as many vias as possible.
The drill diameter of the vias should be 0.33mm,
and the vi as m ust have at least 1 oz. copper platin g
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 5: Multiple small vias (the same
size as the thermal vias discussed in
recommendation 4) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
GND copper closest to the +V copper. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output current loops.
Recommendation 6: AVIN is the power supply for
the small-signal control circuits. It should be
connected to the input voltage at a quiet point. In
Figure 10 this connection is made at the input
capacitor.
Recommendation 7: The layer 1 metal under the
device must not be more than shown in Figure 10.
Refer to the section regarding Exposed Metal on
Bottom of Package. As with any switch-mode
DC/DC conver ter, try not to run sensitive signal or
control li nes undernea th the converter package on
other layers.
Recommendation 8: The VOUT sense point should
be just after the last output filter capacitor . Keep t h e
sense trace short in order to avoid noise coupling
into the node.
Recommendation 9: Keep RA, CA, RB, and R1
close to the VFB pin (Refer to F igure 10). The VFB
pin is a high-impedance, sensitive node. Keep the
trace to this pin as short as possible. Whenever
possible, connect RB directly to the AGND pin
instead of going through the GND plane.
Recommendation 10: Follow all the layout
recommendations as close as possible to optimize
performance. Not following layout
recommendations can complicate designs and
create anomalies different than the expected
operation of the product.
www.altera.com/enpirion, P age 21
06489 March 24, 2015 Rev G
EN6360QI
Design Considerations for Lead-Frame Based Modules
Expose d Me tal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
I n the assem bly process lead fram e construction requ ires that, for m echanica l suppor t, som e of the lead-frame
canti levers be ex posed at the point w here wire-bond or internal passives are attached. This r esults in several
small pads being exposed on the bottom of the package, as shown in F igure 11.
Only the therm al pad and the perim eter pads are to be m echani ca lly or electrica lly connec ted to the P C board.
The PC B top layer under the EN 6360QI should be clear of any m etal (copper pou rs, tra ces, or vi as) ex cept for
the therm al pad. The “shaded-ou t” are a in Figure 11 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aperture should be smaller than the PCB gr ound pad. T his will prevent excess solder fr om
causing bridging between adjace nt pins or othe r exposed m etal under the package. Please consult EN6360QI
Application Notes - Soldering Guidelines for mor e details and recommendations.
Fi gure 11: Lead-Fram e exposed m etal (B ottom Vi ew)
Shaded area hi ghl i ght s ex posed m etal that i s not to be m echani call y or el ectri cal l y connect ed to t he PCB .
www.altera.com/enpirion, P age 22
06489 March 24, 2015 Rev G
EN6360QI
Package and Mechanical
Fi gure 13: EN6360QI Package Di m ensi ons (B ot tom Vi ew)
Packing and Marking I nform ation: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Contact Information
Altera Corporation
101 Innovation Dr ive
San Jos e, C A 95134
Phone: 408-544-7000
www.altera.com
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06489 March 24, 2015 Rev G
