MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY 31 D7 30 D8 1 D5 32 D6 5 29 RS D0 6 28 WEN1 PAF 7 27 WCLK PAE 8 26 WEN2/LD GND 9 25 VCC Q4 20 Q3 19 21 Q5 Q2 18 22 Q6 OE 13 Q1 17 REN2 12 Q0 16 23 Q7 FF 15 24 Q8 RCLK 11 EF 14 REN1 10 * Data Buffer for networks communications. 25 RS 26 D8 27 D7 28 D6 29 D5 1 24 WEN1 D0 2 23 WCLK REN1 6 19 Q7 RCLK 7 18 Q6 REN2 8 17 Q5 Q4 16 20 Q8 Q3 15 5 Q2 14 21 VCC GND Q1 13 22 WEN2/LD 4 Q0 12 3 FF 11 PAF PAE EF 10 APPLICATION 30 D4 D1 OE 9 64words x 9bits (M66850J/FP) 256words x 9bits (M66851J/FP) 512words x 9bits (M66852J/FP) 1024words x 9bits (M66853J/FP) Write and Read Clocks can be independent Advanced CMOS technology Programmable Almost-Empty and Almost-Full flags High-speed : 25ns cycle time Package Available : 32-pin Pastic Leaded Chip Carrier(PLCC) 32-pin Low profile Quad Flat Package(LQFP) 31 D3 32 D2 Outline 32P0(M66850 - 853J) * Memory configuration Outline 32P6B(M66850 - 853FP) D0-D8 - BLOCK DIAGRAM RS 2 D4 4 D2 D1 FEATURES * * * * * 3 D3 PIN CONFIGURATION (TOP VIEW) DESCRIPTION M66850/851/852/853 are very high-speed and clock synchronous FIFO(First-In,First-Out) memories fabricated by high-speed CMOS technology. These FIFOs are applicable for a data buffer as networks and communications. The write operation is controlled by a write clock pin(WCLK) and two write enable pins(WEN1,WEN2). Data present at the data input pins(D0-D8) is written into the Synchronous FIFO on every rising write clock edge when the device is enabled for writing. The read operation is controlled by a read clock pin(RCLK) and two read enable pins(REN1,REN2). Data is read from the Synchronous FIFO on every rising read clock edge when the device is enabled for reading. An output enable pin(OE) controls the states of the data output pins(Q0-Q8). MITSUBISHI FIFOs have four flags (EF,FF,PAE,PAF). The empty flag EF and the full flag FF are fixed flags. The almost empty flag PAE and the almost full flag PAF are programmable flags. The programmable flag offset is initiated by the load pin(LD). RESET LOGIC WCLK WEN1 WEN2 INPUT REGISTER WRITE CONTROL OFFSET REGISTER LD READ POINTER MEMORY ARRAY READ CONTROL WRITE POINTER RCLK REN1 REN2 OUTPUT REGISTER FLAG LOGIC OE EF PAE PAF FF - Q0-Q8 1 MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY PIN and SIGNAL DESCRIPTIONS * VCC One+5 volt power supply pin. * GND One 0 volt ground pin. * RS : Reset(INPUT) When RS is set LOW, internal read and write pointers are set to the first physical location,the output register is initialized to LOW, FF and PAF are set HIGH, EF and PAE are set LOW. A reset is required after power-up before a write operation. * WCLK : Write Clock(INPUT) Data present on D0-D8 is written into the FIFO on the rising edge of WCLK when the FIFO is enabled for writing. * RCLK : Read Clock(INPUT) Data is read from the FIFO on the rising edge of RCLK when the FIFO is enabled for reading. * WEN1 : Write Enable1(INPUT) If the FIFO is configured to allow loading of the offset registers, WEN1 is the only the write enable. When WEN1 is LOW, data on D0-D8 is written to the FIFO on the rising edge of WCLK. If the FIFO is configured to have two writeenables, data on D0D8 is written to the FIFO on the rising edge of WCLK when WEN1 is LOW and WEN2 is High. But if the FF is LOW, data on D0-D8 will not be written to the FIFO. * WEN2/LD : Write Enable2/Load(INPUT) The function of this signal is defined at reset. If WEN2/LD is HIGH at reset, this signal functions as a second write enable(WEN2). If WEN2/LD is LOW at reset, this signal functions as a control to load and read the offset register. If the FIFO is configured to have two write enables, data on D0D8 is written to the FIFO on the rising edge of WCLK when WEN1 is LOW and WEN2 is High. But if the FF is LOW, data on D0-D8 will not be written to the FIFO. If the FIFO is configured to have programmable flags, it is possible to write and read from the offset registers. There are four 9-bit offset registers. Two are used to control the programmable Almost-Empty Flag and two are used to control the programmable Almost-Full Flag. Data on D0-D8 is written to an offset register on the rising edge of WCLK when WEN1 is LOW and LD is LOW. Data on D0 - D8 is written to the offset registers in the following order : PAE LSB, PAE MSB, PAF LSB, PAF MSB. * REN1, REN2 : Read Enable(INPUT) Data is read from the FIFO and presented Q0-8 on the rising edge of RCLK, when REN1 and REN2 are LOW and output port is enabled. If either Read Enable is HIGH,the output register holds the previous data. When the FIFO is empty, the Read Enable signals are ignored. * OE : Output Enable(INPUT) When OE is LOW, the output port Q0-8 is enabled for output. When OE is HIGH, the output port Q0-8 is placed in a high impedance state. * D0-8 : Data Input(INPUT) D0-8 is the 9-bit data input port. * Q0-8 : Data Output(OUTPUT) Q0-8 is the 9-bit data Output port. 2 * EF : Empty Flag(OUTPUT) The Empty flag goes LOW when the read pointer is equal to the write pointer. When EF is LOW, the FIFO is empty and further data reads from the data output are inhibited. EF is synchronized to the rising edge of RCLK. * PAE : Programmable Almost-Empty Flag(OUTPUT) When PAE is LOW, the FIFO is almost empty based on the offset. The default offset is Empty+7. PAE is synchronized to the rising edge of RCLK. * FF : Full Flag(OUTPUT) When FF is LOW, the FIFO is full and further data writes into the data input are inhibited. The Full Flag goes LOW when the FIFO is full of data. FF is synchronized to the rising edge of WCLK. * PAF : Programmable Almost-Full Flag(OUTPUT) When PAF is LOW, the FIFO is almost full based on the offset. The default offset is Full-7. PAF is synchronized to the rising edge of WCLK. MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY OFFSET FLAG LD WEN1 WCLK SELECTION LD REN1 REN2 0 0 Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) 0 1 No Operation 1 0 Write into FIFO 1 1 No Operation Figure 1. Write Offset Register RCLK SELECTION 0 0 0 Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) 0 0 1 1 1 0 1 No Operation 1 1 0 Read from FIFO 1 0 1 1 1 0 1 No Operation Figure 2. Read Offset Register M66850J(64X9-bit) OFFSET REGISTERS 8 7 6 5 4 3 2 1 0 M66852J(512X9-bit) OFFSET REGISTERS 8 7 6 5 4 3 2 1 0 PAE LSB X X X E5 E4 E3 E2 E1 E0 Default Value 007H PAE LSB X E7 E6 E5 E4 E3 E2 E1 E0 Default Value 007H PAE MSB X PAE MSB PAF LSB X X X F5 F4 F3 F2 F1 F0 Default Value 007H X X X X Default Value PAF LSB PAF MSB X X F7 F6 F5 F4 F3 F2 F1 F0 Default Value 007H PAF MSB X X X X Default Value X X X X X X X X X X X X X X M66851J(256X9-bit) OFFSET REGISTERS 8 7 6 5 4 3 2 1 X X X X X X X X X X E8 0 F8 0 0 PAE LSB X E7 E6 E5 E4 E3 E2 E1 E0 Default Value 007H M66853J(1024X9-bit) OFFSET REGISTERS 8 7 6 5 4 3 2 1 PAE MSB X X PAE LSB PAF LSB X F7 F6 F5 F4 F3 F2 F1 F0 Default Value 007H X E7 E6 E5 E4 E3 E2 E1 E0 Default Value 007H PAE MSB PAF MSB X X X X X Default Value PAF LSB X F7 F6 F5 F4 F3 F2 F1 F0 Default Value 007H PAF MSB X X X X Default Value X X X X X X E0/F0 are the least significant bits. X=Don't Care. X X X X X X X X X X X X X X X 0 E9 E8 0 0 F9 F8 0 0 Figure 3. Offset Regigter Location 3 MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI VO Pd Tstg Parameter Supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature Conditions A value based on GND pin Ta=70C Ratings Unit -0.5 - +7.0 -0.3 - VCC+0.5 -0.3 - VCC+0.5 Note -65 - 150 V V V mW C Note : 450mW(32P6B), 550mW(32P0) RECOMMENDED OPERATING CONDITIONS Symbol Vcc GND Topr Parameter Supply voltage Supply voltage Operating ambient temperature Min. 4.5 0 Limits Typ. 5 0 Max. 5.5 70 Unit V V C DC ELECTRICAL CHARACTERISTICS (Ta=0 - 70C, Vcc=5V10%, GND=0V) Symbol VIH VIL VOH VOL IIH IIL IOZH IOZL ICC1 ICC2 CI CO 4 Parameter "H"input voltage "L"input voltage "H"output voltage "L"output voltage "H"input current "L"input current Off state "H"output current Off state "L"output current Operating power supply current Power supply current (Static) Input capacitance Off state output capacitance Test conditions Min. 2.0 Limits Typ. Max. 0.8 IOH = -1mA IOL = 8mA VI = VCC, Any input VI = GND, Any input VO = VCC VO = GND VI = VCC or GND, f = 40MHz, Outputs are open VI = VCC or GND, Outputs are open f = 1MHz f = 1MHz 2.4 0.4 1.0 -1.0 5.0 -5.0 70 500 10 15 Unit V V V V A A A A mA A pF pF MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY SWITCHING CHARACTERISTICS (Ta=0 - 70C, Vcc=5V10%, GND=0V) Symbol tAC tWFF tREF tPAF tPAE tOE tOLZ tOHZ tRSF Parameter Min. 3 Data Access Time Write Clock to Full Flag Read Clock to Empty Flag Write Clock to Almost-Full Flag Read Clock to Almost-Empty Flag Output Enable to Output Valid Output Enable to Output in Low-Z Output Enable to Output in High-Z Reset to Flag and Output Valid time Limits Typ. 3 0 3 Max. 15 15 15 15 15 13 13 25 Unit ns ns ns ns ns ns ns ns ns TIMING CONDITIONS (Ta=0 - 70C, Vcc=5V10%, GND=0V) Symbol tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSS tRSR tSKEW1 tSKEW2 Parameter Min. 25 10 10 6 1 6 1 25 25 25 10 Clock Cycle Time Clock Pulse Width HIGH Clock Pulse Width LOW Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Reset Pulse Width Reset Setup Time Reset Recovery Time Skew time between Read Clock and Write Clock for Empty Flag and Full Flag Skew time between Read Clock and Write Clock for Almost-Empty Flag and Almost-Full Flag Limits Typ. Max. 40 Unit ns ns ns ns ns ns ns ns ns ns ns ns 5.0V 1.1k AC TEST CONDITIONS In Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND - 3.0V 3ns 1.5V 1.5V See Figure 4 D.U.T. 680 30pF Figure 4. Output Load Including Test board and scope capacitances. 5 MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Reset Timing tRS RS tRSS tRSR tRSS tRSR REN1 REN2 WEN1 tRSS tRSR (1) WEN2/LD tRSF EF, PAE tRSF FF, PAE tRSF OE=1 Q0-8 OE=0 NOTE : 1. If during reset WEN2/LD is HIGH,this signal functions as a second enable(WEN2). If during reset WEN2/LD is LOW,this signal functions as an offset register. 6 MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Write Cycle Timing tCLK tCLKH tCLKL WCLK tDS tDH D0-D8 DATA IN VALID tENH tENS WEN1 NO OPERATION NO OPERATION WEN2/(if Applicable) tWFF tWFF FF tSKEW1 (1) RCLK REN1 REN2 NOTE : 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state untill the next WCLK edge. 7 MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Read Cycle Timing tCLK tCLKH tCLKL RCLK tENS tENH REN1 REN2 NO OPERATION tREF tREF EF tAC Q0-8 VALID DATA tOLZ tOHZ tOE OE tSKEW1(1) WCLK WEN1 WEN2 NOTE : 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for EF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state untill the next RCLK edge. 8 MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * First Data Word Latency Timing WCLK tDS D0-D8 D1 D2 D3 D0 (First Valid) tENS WEN1 WEN2 (If Applicable) tFRL (1) tSKEW1 RCLK tREF EF REN1 REN2 tAC tAC Q0-Q8 D0 D1 tOLZ tOE OE NOTE : 1. When tSKEW1minimum specification, tFRL maximum=tCLK+tSKEW1. When tSKEW1minimum specification, tFRL maximum=2tCLK+tSKEW1 or tCLK+tSKEW1. 9 MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Full Flag Timing NO WRITE NO WRITE WCLK tDS tSKEW1 tSKEW1 tDS DATA WRITE D0-D8 tWFF tWFF tWFF FF WEN1 WEN2 (If Applicable) RCLK tENH tENS tENS tENH REN1 REN2 tAC OE LOW tAC Q<8:0> 10 DATA IN OUTPUT REGISTER DATA READ NEXT DATA READ MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Empty Flag Timing WCLK tDS tDS D0-D8 DATA WRITE1 tENS DATA WRITE2 tENH tENS tENH WEN1 tENS tENH tENS tENH WEN2 (If Applicable) tFRL (1) tFRL (1) tSKEW1 tSKEW1 RCLK tREF tREF tREF EF REN1 REN2 LOW OE tAC Q0-Q8 DATA IN OUTPUT REGISTER DATA READ NOTE : 1. When tSKEW1minimum specification, tFRL maximum=tCLK+tSKEW1. When tSKEW1minimum specification, tFRL maximum=2tCLK+tSKEW1 or tCLK+tSKEW1. 11 MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Programmable Full Flag Timing tCLKH (4) tCLKL WCLK tENS tENH tENS tENH WEN1 WEN2 (If Applicable) tPAF PAF Full-(m+1) words in FIFO(1) Full-m words in FIFO(2) tPAF tSKEW2(3) RCLK tENS tENH REN1 REN2 NOTES : 1. PAF offset=m. 2. 64-m words in for M66850, 256-m words in for M66851,512-m words in for M66852, 1024-m words in for M66853. 3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state untill the next rising edge of WCLK. 4. If a write is performed on this rising edge of the write clock,there will be Full-(m-1) words in the FIFO when PAF goes LOW. 12 MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Programmable Empty Flag Timing tCLKH tCLKL WCLK tENS tENH WEN1 tENS tENH WEN2 (If Applicable) PAE n words in FIFO(1) n+1 words in FIFO tPAE tSKEW2 (2) tPAE (3) RCLK tENS tENH REN1 REN2 NOTES : 1. PAF offset=m. 2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then PAE may not change state untill the next rising edge of RCLK. 3. If a read is performed on this rising edge of the read clock, there will be Empty+(n-1) words in the FIFO when PAE goes LOW. 13 MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY * Write Offset Registers Timing tCLK tCLKH tCLKL WCLK tENH tENS LD tENS WEN1 tDH tDS D0-7 PAE OFFSET (LSB) PAE OFFSET (MSB) PAF OFFSET (LSB) PAF OFFSET (MSB) * Read Offset Registers Timing tCLK tCLKH tCLKL RCLK tENH tENS LD tENS REN1 REN2 tAC Q0-7 DATA IN OUTPUT REGISTER PAE OFFSET (LSB) PAE OFFSET (MSB) NOTE : A read and write should not be performed simultaneously to the offset registers. 14 PAF OFFSET (LSB) PAF OFFSET (MSB) MITSUBISHI <DIGITAL ASSP> M66850J/FP, M66851J/FP M66852J/FP, M66853J/FP SRAM TYPE FIFO MEMORY PARAMETER MEASURMENT INFORMATION 3V 1.1K SW1 Qn SW2 CL = 30pF : tAC, tOEN, tODIS 680 Item SW1 SW2 tAC Close Close tPLZ Close Open tPHZ Open Close tPZL Close Open tPZH Open Close Input Pulus Level : 0 - 3V Input Pulus Rising time and Falling time : 3 ns Threshold voltage of Input / Output : 1.5V But tPLZ is decided at 10% of output pulse. tPHZ is decided at 90% of output pulse. Output Load : Including Test board and scope capacitances. VOLTAGE WAVEFORM PROPAGATION DELAY TIMES VOLTAGE WAVEFORM PULSE DURATION TIMES 3.0 V 3.0 V RCK 1.5 V GND tAC tAC 1.5 V GND tW VOH Qn 1.5 V 1.5 V High-Level Input 1.5 V 1.5 V VOL Low-Level Input 3.0 V 1.5 V 1.5 V GND VOLTAGE WAVEFORM ENABLE AND DISABLE TIMES 3V OE 1.5V 1.5V GND tPHZ tPZH 90% Qn 1.5V VOH tPZL tPLZ Qn 1.5V 10% VOL 15