TDC1020 ai 7 High-Speed Monolithic A/D Features Converter 10-Bit Resolution 10-Bit, 20Msps 20Msps Conversion Rate The TRW 1DC1020 is a 20Msps (MegaSample P Overflow Flag e is a 20Msps (MegaSample Per And. _ ; Second} full-parallel (flash) analog-to-digital converter, * Sample-And-Hald Circuit Not Required capable of converting a video signal into a stream of e TTL Digital Interface 10-bit digital words. e Selectable Output Format All outputs of the device are TTL compatible, and will Applications provide the conversion in unsigned magnitude, or two's complement format, and either inverted or noninverted. * Medical Imaging Systems An output signal indicating overflow condition is also Video Data Conversion provided for added flexibility. All digital inputs to the Radar Data Conversion device are TTL compatible. High-Speed Data Acquisition e Process Control! Functional Block Diagram pay NuNY conv m Pr Fors Fa Aus : tor 70.10 ENCODER 31 TRW LSI Products Inc. Phone: (619) 457-1000 TRW Inc. 1990 PO. Box 2472 FAX: (619) 455-6314 40605371 Rev. C- 11/30 La Jolla, CA 92038 Printed in the U.S.A.TDC1020 ANY Functional Description General Information The TDC1020 is a flash analog-to-digital (A/D) canverter in which each of the 1024 comparators has one input biased at one of the transition points of the transfer function and all of the other comparator inputs are connected to the analog input signal. The output of the comparator array is sometimes referred to as a thermometer code as all of comparators biased at voltages more positive than the input voltage will be off and the rest will be on. The thermometer code from the comparator array is encoded into an 11-bit code {10 data bits plus an overflow bit}. The format of the code that is encoded is determined by the format controls NMINV and NLINV so that the data presented to the output latches is in binary, two's compiement or inverted data format. Power and Thermal Management The TDC1020 operates fram two supply voltages, +5.0V and 5.2V. The bulk of the current drawn by the positive supply is returned through the negative supply, however, the positive supply should be referenced to digital ground (DgNp) and the negative supply to analog ground (Agno). All power and ground pins must be connected. The maximum power is drawn at the lower limit of the operating temperature range. When the device is being operated at elevated temperatures, the power dissipation drops, however, thermal management will then be a consideration. The TDC1020 is rated for operation in a 70C ambient temperature in still air. The power dissipation decreases with increasing temperature. TRW specifies the absolute maximum IEE and lec specifications in the Electrical Characteristics Table. The worst case conditions are Vcc =5.25V, VEE= 5.5V and the case temperature equal to 0C. The case temperature of 0C is, however, a transient condition since the device immediately warms up and decreases its power dissipation, upon power up. For typical steady state power dissipation as a function of ambient temperature, please see Figure 7. It is possible to relax the temperature requirements of the device by providing adequate heat sinking. 32 Reference The bias voltages for the comparator array are provided by use of a serial chain of 1024 equal-valued resistors across which the reference valtage is applied. Seven equally separated mid-point adjustment taps are provided to allow the user to optimize the integral linearity of the device. in addition, there are sense leads on the top and bottom of the resistor chain which allow the user to minimize the offset and gain errors of the device. It is recommended that the user drive Rayg, Raa and Rg in order to obtain optimal device performance. One method for driving the references is shown in the Typical Interface Circuit. The reference top and reference bottom sources must be able to source or sink the reference current and since noise on these leads will lead to inaccurate conversions, they should be bypassed with a capacitor to Agnp. There are in addition 4 more reference taps, the use of which is not required to obtain 0.1% integral linearity. It is recommended that these pins be left open (no connection). Format Control There are two inputs provided on the TDC1020 which control the output format of the device. When NMINV is connected to a logic LOW, the MSB is inverted. When NLINV is connected to a logic LOW Da through Dg will be inverted. By using various combinations of these commands the user can select any of the following output data formats: binary, inverted binary, two's complement, inverted two's complement. The Output Coding Table shows the output formats generated for each of the control states. Convert The analog input to the TDC1020 is sampled at a time tsTQ after the rising edge of the CONV signal. The output data from the 1024 comparators is encoded into the proper format and the final result is transferred to the output latches on the next rising edge. This timing is shown in the Timing Diagram (Figure 1). Note that there are minimum LOW and HIGH requirements of the CONV signal {tpyyH. tpyyL) which must be met for proper device operation. In addition, the performance is generally improved if the CONV signal is LOW for as long as possible. A circuit which provides an optimized waveshape CONV signal to the TDC1020 is shown on the Typical Interface Circuit. TRW LSI! Products Inc.TDC1020 atv Analog Input The analog input to the TDC1020 has an equivalent TTL (54/74 LS) unit loads. The outputs hold the previous circuit shown in Figure 2. It should be noted that the data a minimum time tyg after the rising edge of the major component of the input impedance is capacitance, CONV signal. New data becomes valid after a maximum and the input range is 4Vp-p. A low-impedance driving delay time, tp. circuit is recommended for the TDC1020 to obtain good dynamic performance. All analog inputs to the TDC1020 No Connects t ; ; must be connected to insure proper operation of the A/D There are several pins labelled No Connect {NC} which Gu have no electrical connection to the chip. These pins should be connected to Agyp for best noise Outputs performance. The data and overflow outputs of the TDC1020 are TTL compatible, capable of driving four low power Schottky TDC1020 Package Interconnections Signal Signal Type Name Function Value J1 Package Pins GO Package Pins Power Vec Positive Supply Voltage 5.0V 13, 14, 19, 20, 40, 58 | K4, K5, L7, K8, C11, BI Ver Negative Supply Voltage -6.2V 12, 15, 16, 17, 18, 21 L3, L5, K6, L6, K7, L8 Denp Digital Ground 0.0V 10, 11, 22, 23 L2, K3, L10, K10 Aenb Analog Ground 0.0V 43, 55 A10, A3 Reference Rt Reference Resistor, Top 2.0V 59 c2 Rors Overflow Sense 2.0V 57 B2 Rrs Reference Resistor, Tap Sense 2.0V 60 Cl Rui Reference Resistor, 1/8 Tap 1.5 ' 54 B3 Ru Reference Resistor, 2/8 Tap 1.0! 53 Aad Ru3 Reference Resistor, 3/8 Tap 0.5V | 51 AS Rua Reference Resistor, 4/8 Tap 0.0V1 49 B6 Rus Reference Resistor, 5/8 Tap ~0.5V! 47 A8 Rue Reference Resistor, 6/8 Tap 1.0V1 45 AQ Ruz Reference Resistor, 7/8 Tap -1.5V1 44 B9 Rp Reference Resistor, Bottom 2.0V 39 cio Res Reference Resistor, Bottom Sense -2.0V 41 B11 Format Control NMINV Not MSB Invert TTL 63 E2 NLINV Not LSB Invert TTL 28 Ji Convert CONV Convert TTL 36 ou Analog Input VIN Analog Signal Input +2 to -2V | 46, 48, 50, 52 B8, B7, B5, B4 Outputs OVF Overflow TTL 1 El OVF Overflow Complement TTL 2 F2 D, MSB | Most Significant Bit TTL 3 Fi Dy TTL 4 G2 D3 TTL 5 G1 Da TTL 29 H10 Ds TTL 30 Hil Dg TTL 31 G11 Note: 1, Measured values. TRW LSI Products Inc. 33TDC1020 atv? TDC1020 Package Interconnections (cont.) Signal Signal Type Name Function Value J1 Package Pins GO Package Pins Outputs Dy TTL 32 F10 Dg TIL 33 Fil Dg TTL 34 EN Dip LSB Least Significant Bit TTL 35 D10 No Connects NC No Connection Open 6, 7, 8, 9, 24, 25, 26, 27, H2, H1, J2, J1, K1, K2, L4, 37, 38, 42, 56, 61, 62, 64 K9, L9, K11, J10, G10, E10, B10, A7, A6, A2, D2, D1 Output Coding Table Binary Offset Two's Complement True Inverted True Inverted NMINV=1 NMINV=0 NMINV=0 NMINV=1 Input NLINV=1 NLINV=0 NLINV=1 NLINV=0 MSBLSB (OVF} >2,000V 0000000000(1) 1411171111(1) 1000000000(1) OV11411111(1) 2.000V o0c0000000(0) 1411111111(0} 1000000000(0) 0111171111(0) 1.996V 0000000001 (0} 4111111110(0) 1900000001 (0} 0111114110(0} e e e e e e e e e eo e e 0.004V 0111141111(0) 1000000000(0} 41111141110) 0000000000(0) 0.000V 1000000000(0) 0111111111(0) 0000000000(0} 1991111111(0) 0.004V 1000000001 (0) 0111141110(0) 0000000001 (0) 1111111110(0} e e e e e e e e e e e e e eo 1,996V 1111114410(0} 0000000001 (0) 0111111110(0) 1000000001 (0) 2,000V 11111111110) go00000000(0) 0111111111 (0) 1000000000(0) Note: Input voltages are at code centers. 34 TRW LSI Products Inc.TDC1020 artw Figure 1. Timing Diagram < ~ tpwH > tow. > 8 CONV / SAMPLE \ SAMPLE SAMPLE N N+1 | | N+2 ANALOG INPUT ne >| <'s10 piamaoureut | KWKY bey XY DATA XXXX pare XYXYXX Gu > Ho < -> 21162A Figure 2. Simplified Analog Input Equivalent Circuits | Yatas (22%) | Vin O i} ( Vin Cy == ce Rin | Veca VRB G y REFERENCE Cyy'S A NONLINEAR JUNCTION CAPACITANCE FE RESISTOR Vee VppiS A VOLTAGE EQUAL TO THE VOLTAGE ON PIN Rg 21378A Figure 3. Equivalent Input Circuits Figure 4. Output Circuits Convert, NMINV, and NLINV Voc --T TTT T Voc Voc ___ iKo TO 8100 INPUT --T OUTPUT PIN O4 OUTPUT OvREF - [opr 1N3062 OUTPUT EQUIVALENT -__ 21379A LOAD 1 Denp = CIRCUIT TESTLOADFOR == DELAYMEASUREMENTS 21.320 TRW LSI Products Inc. 35= nBas TDC1020 artw Absolute maximum ratings (beyond which the device may be damaged) | Supply Voltages Ver (measured to Denn) -0.5 to +6.0V Veg (measured to Agnp) +5.0 to -6.0V Agnp (measured to Denyp} 1.0 to +1.0V Input Voltages CONV, NMINV, NLINV (measured to Dgnp) 0.5 to +5.5V Vin (measured to Agyp) Vcc to VeeV Any reference (measured to Agno) Veco to VegV Vat (measured to Vpp) -1.0 to +4.4V Output Applied voltage measured to Denn? 0.5 to +5.5V Applied current, externally forced 2:4 1.0 to +6.0mA Short-circuit duration (single output in HIGH state to Ground) on. scseesccssescestesssersssetsesnrecassssseesnetssnssennaetss 1 Second Sense lead current -1.0 to 1.0mA Temperature Operating, ambient 55 to +90C junction +175C Lead, soldering (10 seconds) + 300C Storage 65 to + 150C Notes: 1. Absolute maximum ratings are limiting values applied individually while ail other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. Operating conditions 36 Temperature Range Commercial Extended Parameter Min Nom Max Min Nom Max | Units Vec Positive Supply Voltage 475 5.0 5.25 4.75 5.0 5.25] V VEE Negative Power Supply Voitage -49 5.2 -5.5 -49 -5.2 -55 | V VAGND Analog Ground Voltage {measured to Deny) -0) 0.0 0.1 -0.1 0.0 0.1 V tpwL CONV Pulse Width, LOW 22 22 ns tpwH CONV Pulse Width, HIGH 18 20 ns Vib Input Voltage, Logic LOW 0.8 08 | V VIH Input Voltage, Logic HIGH 2.0 2.0 V lat Output Current, Logic LOW 4.0 40 mA igh Output Current, Logic HIGH 400 400 pA Vem2 Reference Tap, 1/4-Scale 0.8 1.0 1.2 0.8 1.0 12 7 V Vama Reference Tap, 1/2-Scale 0.2 0.0 0.2 ~0.2 0.0 02] V VrMs Reference Tap, 3/4-Scale 0.8 1.0 1.2 -08 -1.0 -12 7 V Vat Most Positive Reference Voltage 1.8 2.0 2.2 18 2.0 22] V Vep Most Negative Reference Voltage -18 2.0 -22 -18 -2.0 -22 1 V VeTVrp Reference Voltage Differential 3.6 4.0 44 3.6 4.0 441, V TRW LSI Products Inc.TDC1020 71try IXY Operating conditions (cont.) Temperature Range Commercial Extended Parameter Min Nom Max Min Nom | Max Units Vin Input Voltage Range VrB +2.0 Vet VRB +2.0 Vet | V Ta Ambient Temperature, C-Grade 0 70 C Tc Case Temperature, V-Grade 55 125 C Electrical characteristics within specified operating conditions Temperature Range Commercial Extended Parameter Test Conditions Min Max Mia Max | Units lec Total Positive Supply Current Vec= Vee = Max 850 850 mA leg Total Negative Supply Current | Veg =Max ~ 500 500 mA IREF Reference Current Vat. Vag =Nom 50 50 mA Recep Reference Chain Resistance Vet. Vap=Nom 80 80 Ohms Rin Analog Input Resistance Vat Vag= Nom, Vin=Vap 3000 2000 Ohms Cy Analog Input Capacitance Vat VRp=Nom, Vin=Vprp 300 300 pF leg Input Constant Bias Vee = Max 2 3 mA Vie Input Current, Logic LOW Vec=Max, Vj=0.5V 50 50 pA tH Input Current, Logic HIGH Vee = Max, Vj=2.4V 100 100 pA I, Input Current, Maximum Vec= Max, Vj =5.25V 100 100 pA Vo Qutput Voltage, Logic LOW Vec= Min, lp, =Max as O51 V Vou Output Voltage, Logic HIGH Vec=Min, Io, =Max 24 24 V los Short-Circuit Output Current Vcc =Max, output HIGH, one pin to 35 -35 mA ground, one second duration max. C Digital Input Capacitance Ta =25C, f= 1MHz 15 1 pF Switching characteristics within specified operating conditions Temperature Range Commercial Extended Parameter Test Conditions Min Max Min Max Units Fe Maximum Conversion Rate Veg =Min, Vcc =Min 20 20 Msps tgyq Sampling Time Offset Veg =Max, Voc =Max 3 17 3 17 ns tp Output Delay Vee = Max, Voc = Max 37 43 ns tuo Output Hold Time Vee=Max, Voc = Max 5 5 ns TRW LSI Products Inc. 37TDC1020 arte System performance characteristics within specified operating conditions Temperature Range Commercial Extended Parameter Test Conditions Typ Min Max Min Max | Units Ey Linearity Error, Integral Reference Taps Open +0.1 +0.2 +021 % Ey, Linearity Error, Integral Reference Taps Adjusted +0.05 +0.1 0.07 % Etp Linearity Error, Differential Reference Taps Open +0.05 +0.1 +015 % cS Code Size 5 225 5 225 % Nominal Egt Offset Error, Top 25 - 30 mV Egp Offset Error, Bottom -30 -35 mV Teo Offset Error Tempco +10 +20 | pAISC tr Transient Response Full-Scale Input Step, 20 30 30 ns Settling to +32 LSBs BW Full-Power Bandwidth Full-Scale Input 10 5 MHz SNR Signal-to-Noise Ratio Note 1 Fin= 1.0MHz 60 58 58 dB Fi = 2.0MHz 59 56 56 dB Fin =5.0MHz 56 52 52 dB Fiy = 8.0MHz 54 47 dB Fin = 10.0MHz 52 43 dB SINAD Signal-to-Noise And Distortion | Note 1 Fin = 1.0MHz 59 55 52 dB Fin = 2.0MHz 58 52 52 dB Fyny = 5.0MHz 54 48 45 dB Fin=8.0MHz 48 41 dB Fin = 10.0MHz 43 39 dB THD Total Harmonic Distortion Note 1 Fy = 1.0MHz - 66 58 53 dBc Fin = 2.0MHz 64 ~56 53 dBc Fin = 5.0MHz ~- 58 ~52 -46 dBe Fin = 8.0MHz --50 ~ 43 dBc Fin= 10.0MHz 44 ~41 dBc SFDR Spurious-Free Dynamic Range | Note 1 Fin=1-0MHz 70 53 53 dB Fin = 2.0MHz 68 54 54 dB Fin = 5.0MHz 63 48 48 dB Fyn = 8.0MHz 55 40 dB Fiyy = 10.0MHz 48 35 dB Eap Aperture Error 50 ps DP Differential Phase Fg=4x NTSC Subcarrier, 0.3 0.5 Degree Reference Taps Adjusted DG Differential Gain Fg=4 x NTSC Subcarrier, 0.8 1.0 % Reference Taps Adjusted Note: 1. Fo=20Msps, Reference Taps Adjusted, Vap=Ver=Nom, Ty = 25C. $ CO YEE A 33 TRW LSI Products Inc.TDC1020 IX Calibration Calibration of the TDC1020 consists of adjusting the reference taps so that the converters integral linearity, gain and offset errors are minimized. To minimize the offset errors the sense leads must be used properly. The sense leads are not designed to carry very much current (<1mA} and should therefore be used in a feedback loop to a high-impedance input such as that shown in the Typical Interface Circuit. \When a circuit similar to that in the Typical Interface Circuit is used for generating the reference voltages, calibration can be achieved with the following procedure: |. Apply an input to the input amplifier which is 1/2 LSB less than full-scale (A/D input=1.998V) and adjust the gain so that the output of the A/D is toggling between full-scale and one LSB below full- scale (1111111111 and 1111111110 for binary conversions). 2. Apply an input to the input amplifier which is 1/2 LSB greater than zero-scale (A/D input= 1.998V] and adjust Vjg via the Vap pot so that the output of the A/D is toggling between 0 and 1 (0000000000 and 0000000001 for binary conversions). The A/D converter will now be calibrated to provide accurate conversions throughout its input range. To optimize the integral linearity of the device set up the Subtractive Ramp Test described on page 6 of the TRW Applications Note TP-30, Understanding Flash A/D Converter Terminology, then adjust the mid-point taps to minimize the bow in the error curve. Typical Interface A Typical Interface Circuit is shown of the TDC1020. The analog input amplifier, a THC4231, is used to directly 40 drive the A/D converter. This amplifier is set up to have a gain of four and will provide the recommended +2 to 2V input signal to the TDC1020 when it has a 1Vp-p input signal. All four analog input pins are connected in parallel to decrease the parasitic inductance. An LM313 is used to provide a stable reference voltage which is buffered by a dual op-amp, generating Vat and Vpp. Both op-amps have their outouts buffered by an emitter follower to decrease the output impedance seen by the reference resistor chain. To minimize noise coupling into the reference resistor chain, bypass capacitors have been added, bypassing the reference taps to ground. Since capacitive coupling from the digital signals to the analog input will adversely affect the converter perform- ance, careful attention to board layout is recommended. As is true with most bipolar integrated circuits, the substrate of the TDC1020 (Vef) must be the most negative potential applied. This rule applies for all conditions of temperature, signal level and power supply sequencing. In many systems, the voltage reference generators and input driving amplifier are powered from voltages greater than the +5 and 5.2V of the TDC1020. Whenever this situation occurs, it is always possible for the Veg inputs of the TDC1020 to be positive with respect to the Vjjy or VaR inputs when power supplies are cycled ON and OFF. To protect the TDC1020 from latch-up due to substrate bias, TRW recommends the use of a 1N5818 Schottky diode connected between Veg and Vij and another between Veg and Vap with the anode of each diode connected to Veg. The diodes. prevent Vjyy and VpT from going more than O.4V mare negative than VeE. This protection circuit is shown in Figure 5. TRW LSI Products Inc.TDC1020 aw Figure 5. Typical Interface Circuit +f ra Our] Voc +5V > nN. 1OuF Lior + 1OuF |+ hy ae C O1pF | Otek th mer | A 10, 11, sy 13,14| 19,20] 40,58{ [2212 - pp Veo Yee Yeo Dgnp y v v a 16 [.7 Veg GND 82.50 Vw ove o tol v ow 2} 4 Sy ANALOG 1N5818 IN . 20 20 Vp-p "N tse), > asia 51.40 43 > | ee Agno 0 14 ao sap 55 13 1 po Agno Dg 5 5D 50 2 14 ey Cir | Otue 24 Rr p, 2 6D 60 > 9 Vv } cK crn}-~< oPz21 a Th N22 sol o.tue T TDC1020 ; ity = 1000 otuF] 0.01 uF TT 20K0 a, 6 , rh OFS Voc GND R 30 3 2 GAIN ADJ Rt 53] "M2 Ds 1D 10> I 10-TURN . Tose Dg EL 4 20 20> + 2 sp-49] 2 Dy 32 __} 6 D 30 Ly, . ; tt M4 3 ny. msm 1, : Tocat69 f y | oF Dg 4D 4a Pou 34 13 2 oar 4 LINEARITY Dg sD sop 45 {Ka Gn 35 4 5 ga2ko | 19-TuRN al (LSB) D4 60 6a} > T Ras 8 ik cir p< aa 1000 6 To.tuF ; Ay cLock 1 on 1 Rp CONV ? INPUT > ll Vee Yee Ve 12,15] 1,17 [18,21 rl. Tl TL Ver: SV aon EE + : , ger pu Eu Lt v Ri, R22KQ 10- TURN POTENIOMETER oo INDUCTORS: FAIR-RITE #2743 001112 ANALOG 10 GROUND 7 d e DIGITAL GROUND > | 21377A TRW LSI Products Inc. 41TDC1020 7 AX Evaluation Board The TDC1020E1C is a Eurocard-style printed circuit board designed to optimize the performance of, and to aid in the evaluation of the TDC1020 A/D converter. The board dimensions are 100mm x 160mm with a standard 64 pin double-row DIN male connector installed. A comple- mentary 64 pin double-row DIN female connector is included with the board. The circuitry on the board includes reference voltage generators, wideband video input amplifier, and a TDC1012 12-bit D/A converter which may be used in evaluating certain parameters of the TDC1020. The board employs only two conducting sides. Most of the circuit interconnections are on the bottom of the board while the top is mostly solid ground plane. SMA connectors are installed on the board to facilitate analog I/O and clocks. The board is calibrated and tested at the factory and is supplied complete with TDC1020 and TDC1012 installed. Power and Ground Four power supply voltages are required for the operation of the TDC1020E1C: Voc =+5V, Veg= 5.2V, V+=+415V end V=15V. All power inputs are decoupled to a single solid ground plane. All GND pins of the board are connected to the ground plane and it is recommended that all GND pins be used. Voltage Reference Generator The TDC1020E1C has two voltage reference generator circuits for driving the RT and RB terminals of the TDC1020. A variable +2.0V is applied to RT from U3A and Q2. A variable 2.0V is supplied to RB fram U3B and Q1. The GAIN potentiometer, R11, provides + 10% adjustment range to both RT and RB voltages. Video Input Amplifier The input amplifier of the TDC1020E1C, U4, is a THC4231 current-feedback amplifier and has been designed to accept +0.5V input range and translate that signal to the +2 to ~2V range of the TDC1020. The output of this amplifier can be monitored at the P6 SMA connector which is connected to the Vij) terminals of the TDC1020 through a 4700 resistor. The OFFSET potentiometer, R10, gives a +0.5V offset adjustment range to the board. 42 A/D Converter Inputs The clock to the TDC1020, CONV, is normally brought onto the board through the SMA connector labeled CONV P5." By installing jumper J12, this signal is routed through the edge connector pin B3. A terminating resistor, R25 may be installed on the board for termi- nating a CONV signal cable. The NMINV and NLINV inputs to the TDC1020 are pulled HIGH with resistors and may be pulled LOW by installing jumpers J15 and J17, The analog signal input to the TDC1020E1C is brought onto the board by way of the SMA connector labeled P3" through J9 and J10. A terminating resistor, R7, is included on the board for terminating a 50Q analog input signal cable. Jumpers J10 and J11 permit the analog input signal to enter the board from edge- connector pin B28. A/D Converter Data Outputs and D/A Converter Data Inputs The ten data outputs of the TDC1020 are brought to edge-connector pins B5 through B14. These pins are located directly across the edge-connector from the corresponding data inputs of the TDC1012 D/A converter to simplify connection of A/D outputs to D/A inputs. D/A Converter Inputs The clock to the TDC1012 is normally brought onto the board through an SMA connector labeled 'P9". This signal may also be brought onto the board from edge- connector pin B29 by installing jumper J21. A location for a terminating resistor, R57 is provided for clock cable termination. D/A converter outputs are brought to SMA connectors labeled OUT+ P7" and OQUT P8" Load resistors of 51.10 are provided on the board to facilitate 500 cable connection to the board. Potentiometer R58 is used to adjust the reference voltage to the TDC1012. This voltage is adjusted to 1.0V as part of the factory test and calibration procedure. Removing jumper, J20, will put the TDC1012 into feedthru (unclocked) mode. This eliminates the require- ment for a D/A clock signal, but will degrade the fidelity of the TDC1012 reconstruction. TRW LSI Products Inc.TDC1020 arty THC4940 Track/Hold Option The TOC1020E1C has been designed to accomodate the THC4940 Track/Hold amplifier in the analog signal path prior to the THC4231 wideband input amplifier. To install the THC4940 on the board jumper connections outlined on the Jumper Options Table should be followed. The TDC1020E1C can be configured to accept the analog input from either the edge-connector or the P3 SMA. The Track/Hald timing signal is configured for TTL compatibility with the use of J2 and J8 which bias pin 2 of the THC4940 to TTL threshold. J5 applies the Hold/Track timing signal to pin 1 of the THC4940. The Hold/Track timing signal can be routed from SMA P2 or the edge-connector. TDC1020E1C Eurocard Edge Connector Pinout GND A32 GND A31 GND A30 GND A29 GND A28 GND A27 GND A26 GND A25 GND A24 GND A23 GND A22 GND A21 GNO A20 GND A19 GND Alg GND At? GND A116 GND At5 D/A Dy MSB A14 DIAD, A13 D/A D3 Al2 DIAD, All DAD, Ato DIADg A9 DAD, As DIADg AZ DIA Dg AG DIA Dig AS DIA Dy, A4 DIA Dy LSB A3 GND A2 GND Al B32 B31 B30 B29 B28 B27 B26 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 Bid B14 B13 B12 B11 B10 BS BB BI B6 BS B4 B3 B2 BI V- (-15V) AMP V+ (4+15V} AMP OVF D/A CLK INPUT ANALOG INPUT NC Souriau NC Souriau NC Souriau DIA CLK NC NC NC NC NC Vee (+5) NC NC NC AID Dy MSB AID Dp AID D3 AID Dy AID Ds, AID Dg AID Dy AID Dg AID Dg AID Djg LSB OE A/D CONV T/H DIGITAL INPUT Veg (-5.2V) TRW LSI Products Inc. Robinson-Nugent Robinson-Nugent Mating Connectors for TDC1020E1C 932507-2 932507-1 RNE-64BS-W-TG30 RNE-64B8-S-1G30 8609-264-6115-7550E1 8609-264-6114-7550E1 8609-264-6813-7590E1 Wire-wrap Solder tail Wire-wrap Solder tail Wire-wrap Solder tail Solder tail, right-angle bend 43TDC1020 a, td a vw Jumper Options Table Function SMA-Connector Edge-Connector Termination Analog Input Signal for P3, use J9, J10 for B28, use J10, J11 R7 AID Converter CONV for P5, use J13 for B3, use J12, J13 R25 D/A Converter CLK P9 for B29, use J21 R57 for B3, use J12, J13, J14 R25 T/H Analog Input for P3, remove J9, J10, J11 for B28, use J9, Jti R7 T/H Timing Input for P2, use J4 for B2, use J3 J6, Ri TDC1020E1C Silkscreen Layout Mamie | eS. ai ale oo Ou 4 rf U4 8 pa Pl ae 18 w DONOM*AWN 8 2% a g r ~ Cw 8 OxyP yP US pad Ta "Up C36 o> 1G) ed 08 8 0. TDC1020E1C 9 ae Dw TRW LS! Products Inc. ) Te ; C8 2 Ff Apa 08 P4 us tii, Q OM BOARD 4@X@2510 REV. D ASSEMBLY 9@x@5808 REU.[_] ow sl TER 44 TRW LSI Products Inc.tw TDC1020 TDC1020E1C Component Side Layout mine) oO OO% 7000020000 go fase ooo 00 lelelerelele) 999 OlelOlOIRIelelelelelerelelele) ee ( [e) 2 O 1020E1C Circuit Side Layout " ie TDt : d | ly, I 45 TRW LSI Products Inc.TDC1020 atv TDC1020E1C A/D Converter Schematic Diagram a5v (P1631) dt a) S SN cw COG 22 281 ie et Ly 38. c 8 E4 u 0. an cto THCA231 a1 ! wt R Bz v 6 5 WZ a az. so 0.08 8 GND *ec1 ecz ans x % pelt ANALOG d uw 0 q inpur Yn qwesew WV * ne a u2 i eno ~Yec1 TRACK HOLD GND GND ~tc2 @ a 5 ta ne ee | | Wy . i L 7 ae can L L es? sms aS ourruy see San cs ys ce > 150 eH > See Lo) ros Jon WPUT an m0 mi Ba< qT ay mK ne v hgh {yoo = a OFFSET | = at it ont 68 ssv (Pt Baz us Gos A irroosci-12 1 ( ier @) AS * "1 +5 8 a H INPUT C_-- P2 % #57 1s Log ww Bo ra SL 150 a6 iV +5 (Pt B18} een n rir 1 Ie a 52 (Pt at ) Veen conv (#1 83} macix (P1679) A (fr) Al, A2, A15, AVG, A1?, A18, At9, A20, AZ1, A22, AZ3, suo % 2A, ATS, AS. ADT, AZB, AIG, AIO, At, AIZ 46 TRW LSI Products Inc.TDC1020 aitw == cep Or oo ay. NOTE. |1) SEE ASSEMBLY SPECIFICATION DASH NO FOR ACTUAL CKT CONFIGURATION . UNUSED REFERENCE DESIGNATORS: U. c NOTE CONNECT OIRECTLY 06 Reeaa 10 818-2 inate 3, we 0P221 Yeca B38 Aw WW BS PI) DygisB B56 PI) Dy 87 Pi) Dy BE PI) D, CHD 07 Bi Pt) Ds mus BIY PI) Dy Biz PI) 05 72N2222 B13 Pt) D, 814 P1) 0, MsB Bx PI) OVE Ata P1) 0) MSB AI3_ Pt) D, 12 Pt) 0, A PL) Dy _____| AWD PI) Og, Aa PI) 0, . ry aa Pt) D, u AAS A7_ PI) Og rep O~ AG Pt) Dy roof mon MA PI) Oy Al Pt) D,2isB a) = Tha 1P-3 =v mK vAMZ a VRMG yo TF2 o R36 935 VRBS tap oJ? tao 28 f 3 a2 Teo om rep 7 TeD 19 R27 AMA TED " 8 cep B34 30 x 2k a SCALE elie del me WAM Dy Bz Dy Dy 05 Dg Oy Dy Dy Dyy Myy O42 UZA/A, RI ao A coAY Ogun ie ve o> 1? opz21 VRBS 1 ft ce een rea come ftr ners ouT- Agno outs os | ow nor tao | Teo : a }$"4 os it om Veen o1 b ours ? 01 our CT ur KTreosH-1.2 TRW LSI Products Inc. 47TDC1020 Trt yi vy Ordering Information Product Temperature Range Screening Package Package Number Marking TOC1O20J1C STDTp =0C to 70C Commercial 64 Pin Hermetic Ceramic DIP 1020J1C TDC1O20J1V EXT-Te= 55C to 125C Military 64 Pin Hermetic Ceramic DIP 1020J1V TDC1020G0C STD-Tp =0C to 70C Commercial 68 Pin PGA 1020G0C TOC1020G0V EXT-Tp= ~55C to 125C Military 68 Pin PGA 1020G0V TDC1020E1C STD-Ta=0C to 70C -- Eurocard Format Board With A/D Converter TDCt020E1C All parameters in this specification are guaranteed by design, characterization, sample testing or 100% testing, as appropriate. TRW reserves the right to change products and specifications without notice. This information does not convey any license under patent rights of TRW inc. or others. Life Support Policy ~ TRV LS! Products Inc. components are not designed for use in fife support applications, wherein a failure or malfunction of the component can reasonably be expected to result in personal injury. The user of TRW LSI Products inc. components in life support applications assumes all risk of such use and indemnifies TRW LS! Products Inc. against all damages. Pin Assignments 68 Pin Grid Array GO Package Pin | Name | Pin | Name Pin | Name | Pin | Name A2 | NC Bo | Ruz Fil | Dy Ka | Vec A3_ | Agno | 810 | NC Fil | Dg K5 | Vec Ad | Ryo | Bit | Reg GI | D3 KB | Veg A5 | Rug | Cl | Rrs 62 | Do Kk? | Veg AB} NC C2 | Rr Gio} NC K8 | Vec Al NC Cid | Rp G11 Dg kg NC A8 Rus Ci Vec H1 NC K10 Oeno AS | Rug | Ot | NC H2 | NC Ki | NC All | Agnp | 02 {| NC H10 | Dg L2 | Deno Bi Vec D10 Dio LSB H11 Dr L3 VEE B2 Rors D011 | CONV Jl NC L4 NC B3 | Ryy | Et | Ove v2 | NC L5 | Veg 84 | Vy | 2 | NMINV | JiG | NC t6 | Veg Bb VIN E10 | NC Ju NLINV 7 Vec Be | Rug | Ett | Dg KI | NC L8 | Veg B7 | Vin Fl | D, MSB} Kz | NC tg | NC BB | Vin F2 | OVF K3 | Denn | L10 | Dgnp olf SOGOGSS OS C3 pase testet oD | NES sciset TOP ee VIEW oon Ne Key aes, ' (See bottom we TTT of package) OOS ke CR A BcoDEFGHMAJKEL 48 Deno 0 Deno 1 Veg 120 Veg 0 Vec QJ Veg 6 Vee 16 f] Vee wv Ver 190 Vec iL Voc 20 Veg 210] Denn 220 Denn 23 Nc 240] NC 25 {] Ne 26] Ne 27] NEINV 28 [] D, 20 ds iQ] b, 32] r) 64 r] 63 r] 62 | 64 r] 60 1) 59 r] 58 [57 | 56 r] 55 | 54 [] 53 1) 52 1 51 1} 50 r} 49 r] 48 1] 47 r] 46 | 45 1 44 1) 43 1 42 r 41 1Z 1] 39 | 38 1] 37 [| 36 1] 35 HE [] 33 TRW LSI Products Inc. NC NMINV NC Fa NC NC CONV D4p (LSB) Dg Dg 21385A 64 Pin Hermetic Ceramic DIP J1 Package