REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
A
Changes are in accordance with the notice of revision 5962-R228-96. - bjm 96-09-30 Monica L. Poelking
B
Redrawn with changes. Update the boilerplate to the current requirements of
MIL-PRF-38535. - jak 08-03-12 Thomas M. Hess
C
Add footnote 12/ for test condition of total power supply current (ICCT) to table I.
- LTG
10-04-19
Thomas M. Hess
REV
SHEET
REV C C C C C
SHEET 15 16 17 18 19
REV STATUS REV C C C C C C C C C C C C C C
OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A PREPARED BY
Joseph A. Kerby
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 4321 8-3990
http://www.dscc.dla.mil
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
CHECKED BY
Thomas J. Ricciuti
APPROVED BY
Monica L. Poelking
MICROCIRCUIT, DIGITAL, FAST CMOS,
EIGHT INPUT UNIVERSAL SHIFT REGISTER
WITH THREE-STATE OUTPUTS, TTL
COMPATIBLE INPUTS AND LIMITED OUTPUT
VOLTAGE SWING, MONOLITHIC SILICON
DRAWING APPROVAL DATE
93-08-10
REVISION LEVEL
C
SIZE
A CAGE CODE
67268
5962-92216
SHEET
1 OF
19
DSCC FORM 2233
APR 97 5962-E277-10
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92216
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing documents t wo product assur ance class levels consisting of hi gh reliability (device class es Q and
M) and space application (de vice class V). A choice of case outlines and lead finishes ar e available and are reflected in the Part
or Identifying Number (PIN). When availa ble, a choice of Radiation Hardness Assura nce (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962 - 92216 01 M R A
Federal
stock class
designator
RHA
designator
(see 1.2.1)
Device
type
(see 1.2.2)
Device
class
designator
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
\ / (see 1.2.3)
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked dev ices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a n on-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number Circuit function
01, 02 54FCT299T Eight input universal shift register with three-state
outputs, TTL compatible inputs and limited output
voltage swing
03, 04 54FCT299AT Eight input universal shift register with three-state
outputs, TTL compatible inputs and limited output
voltage swing
05, 06 54FCT299CT Eight input universal shift register with three-state
outputs, TTL compatible inputs and limited output
voltage swing
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class Device requirements docum entation
M Vendor self-certification to the requireme nts for MIL-STD-883 compliant, non-
JAN class level B microcircuits in accordance with MIL-PRF-38535, append ix A
Q or V Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as desi gnated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
R GDIP1-T20 or CDIP2-T20 20 Dual-in-line
S GDFP2-F20 or CDFP3-T20 20 Flat pack
2 CQCC1-N20 20 Leadless-chip-carrier
1.2.5 Lead finish. The lead finish is as speci fied in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92216
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 3
DSCC FORM 2234
APR 97
1.3 Absolute maximum ratings. 1/ 2/ 3/
Supply voltage range (VCC) ....................................................................... -0.5 V dc to +7.0 V dc
DC input voltage range (VIN) .................................................................... -0.5 V dc to VCC + 0.5 V dc 4/
DC output voltage range (VOUT) ................................................................ -0.5 V dc to VCC + 0.5 V dc 4/
DC input clamp current (IIK) (VIN = -0.5 V) ................................................. -20 mA
DC output clamp current (IOK) (VOUT -0.5 V and +7.0 V) ........................... +50 mA
DC output source current (IOH) (per output) ............................................ -30 mA
DC output sink current (IOL) (per output) ................................................. +70 mA
DC VCC current (ICC) ............................................................................... 316 mA
Ground current (IGND) .............................................................................. +716 mA
Storage temperature range (TSTG) ............................................................ -65C to +150C
Case temperature under bias (TBIAS) ...................................................... -65C to +135C
Maximum power dissipation (PD) .............................................................. 500 mW
Lead temperature (soldering, 10 seconds) ............................................... +300 C
Thermal resistance, junction-to-case (JC) ................................................ See MIL-STD-1835
Junction temperature (TJ) ....................................................................... +175C
1.4 Recommended operating conditions. 2/ 3/
Supply voltage range (VCC) ...................................................................... +4.5 V dc to +5.5 V dc
Input voltage range (VIN) .......................................................................... +0.0 V dc to VCC
Output voltage range (VOUT) ..................................................................... +0.0 V dc to VCC
Maximum low level input voltage (VIL) ..................................................... 0.8 V
Minimum high level input voltage (VIH) ..................................................... 2.0 V
Case operating temperature rang e (TC) ................................................... -55C to +125C
Maximum input rise or fall rate (t/V):
(from VIN = 0.3 V to 2.7 V, 2.7 V to 0.3 V) .............................................. 5 ns/V
Maximum high level output current (IOH):
Device types 01, 03, and 05 ................................................................... -12 mA
Device types 02, 04, and 06 ................................................................... -6 mA
Maximum low level output current (IOL) .................................................... 32 mA
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ Unless otherwise noted, all voltages ar e referenced to GND.
3/ The limits for the parameters specified herein shall apply over the full specified VCC range and case temperature range of
-55C to +125C.
4/ For VCC 6.5 V, the upper limit on the range is limited to 7.0 V.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92216
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 4
DSCC FORM 2234
APR 97
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and han dbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-385 35 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents ar e available online at https://assist.daps.dla.mil/quicksearch/ or www.dodssp.daps.mil or from
the Standardization Document Order Desk, 700 Robbins Avenue, Buildin g 4D, Philadelphia, PA 19111-5 094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicabl e laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requ irements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specif ied herein or as modified in the device manufacturer's Quality Man agement (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in acc ordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and ph ysical dimensions shall b e as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Truth tables. The truth tables shall be as specified on figure 2.
3.2.4 Logic diagram. The logic diagram shall be as specified on figur e 3.
3.2.5 Ground bounce load circ uit and waveforms. The ground bounce load circuit and waveforms shall be as specified on
figure 4.
3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5.
3.3 Electrical performance characteristics and postirradiation par ameter limits. Unless otherwise specified h erein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature rang e.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are defined in table I.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92216
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 5
DSCC FORM 2234
APR 97
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the devic e. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF - 38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as requ ired in MIL-PRF-38535, appendi x A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of complianc e shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of suppl y in MIL-HDBK-1 03
(see 6.6.2 herein). The certificate of complia nce submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirement s of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38 535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product
(see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acqu iring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the optio n of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 40 (see MIL-PRF-38535, appendix A).
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92216
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s.
Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/
-55C TC +125C
+4.5 V VCC +5.5 V
unless otherwise specified
Device
type VCC Group A
subgroups Limits 3/ Unit
Min Max
High level output
voltage
3006
VOH1
4/ For all inputs affecting output under test
VIN = VIH = 2.0 V or VIL = 0.8 V
For all other inputs VIN = VCC or GND
IOH = -300 A
01, 03,
05 4.5 V 1, 2, 3 3.0 VCC-0.5 V
02, 04,
06 2.7 VCC-0.5
VOH2 For all inputs affecting
output under test
VIN = VIH = 2.0 V or VIL =0.8 V
For all other inputs
VIN = VCC or GND
IOH = -12 mA 01, 03,
05 4.5 V 1, 2, 3 2.4 VCC-0.5 V
IOH = -6 mA 02, 04,
06 2.4 VCC-0.5
IOH = -12 mA 2.0 VCC-0.5
Low level output
voltage
3007
VOL1
4/ For all inputs affecting output under test
VIN = VIH = 2.0 V or VIL = 0.8 V
For all other inputs VIN = VCC or GND
IOL = 300 A
All 4.5 V 1, 2, 3 0.20 V
VOL2 For all inputs affecting output under test
VIN VIH = 2.0 V or VIL = 0.8 V
For all other inputs VIN = VCC or GND
IOL = 32 mA
All 4.5 V 1, 2, 3 0.55 V
Three-state output
leakage current
high
3021
IOZH
5/ 6/
OEn = VIH or VIL
VIH = 2.0 V
VIL = 0.8 V
For all other inputs VIN = VCC or GND
VOUT = VCC
01, 03,
05 5.5 V 1, 2 0.1 A
3 2.0
02, 04,
06 1, 2 1.0
3 10.0
Three-state output
leakage current
low
3020
IOZL
5/ 6/
OEn = VIH or VIL
VIH = 2.0 V
VIL = 0.8 V
For all other inputs VIN = VCC or GND
VOUT = GND
01, 03,
05 5.5 V 1, 2 -0.1 A
3 -2.0
02, 04,
06 1, 2 -1.0
3 -10.0
Negative input
clamp voltage
3022
VIC- For input under test, IIN = -15 mA 01, 03,
05 4.5 V 1, 2, 3 -1.2 V
For input under test, IIN = -18 mA 02, 04,
06 -1.3
Input current
high
3010
IIH For input under test,
VIN = VCC
For all other inputs,
VIN = VCC or GND
01, 03,
05 5.5 V 1, 2 0.1 A
3 1.0
02, 04,
06 1, 2 1.0
3 5.0
Input current
low
3009
IIL For input under test,
VIN = GND
For all other inputs,
VIN = VCC or GND
01, 03,
05 5.5 V 1, 2 -0.1 A
3 -1.0
02, 04,
06 1, 2 -1.0
3 -5.0
Input capacitance
3012 CIN
7/ See 4.4.1c
TC = +25C All GND 4 10 pF
Output capacitance
3012 COUT
7/ See 4.4.1c
TC = +25C All GND 4 12 pF
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92216
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 7
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s - Continued.
Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/
-55C TC +125C
+4.5 V VCC +5.5 V
unless otherwise specified
Device
type VCC Group A
subgroups Limits 3/ Unit
Min Max
Short circuit output
current
3005
IOS
8/ For all inputs, VIN = VCC or GND
VOUT = GND All 5.5 V 1, 2, 3 -60 -225 mA
Dynamic power
supply current ICCD
4/ 9/ Outputs open All 5.5 V 4, 5, 6 0.25 mA/
MHz•Bit
Quiescent supply
current delta,
TTL input level
3005
ICC
10/ For input under test
VIN = VCC - 2.1 V
For all other inputs
VIN = VCC or GND
All 5.5 V 1, 2, 3 2.0 mA
Quiescent supply
current, output high
3005
ICCH For all other inputs, VIN = VCC or GND All 5.5 V 1, 2, 3 1.5 mA
Quiescent supply
current, output high
3005
ICCL For all other inputs, VIN = VCC or GND All 5.5 V 1, 2, 3 1.5 mA
Quiescent supply
current, output high
3005
ICCZ
5/ For all other inputs, VIN = VCC or GND All 5.5 V 1, 2, 3 1.5 mA
Total supply
current ICCT
11/ 12/ Outputs open
OE1 = OE2 = GND
MR = VCC
S0 = S1 = VCC
DS0 = DS7 = GND
fCP= 10 MHz
50% duty cycle
One bit toggling
fi = 5 MHz
50% duty cycle
For nonswitching inputs
VIN = VCC or GND
For switching
inputs,
VIN = VCC or
GND
All 5.5 V 1, 2, 3 4.0 mA
For switching
inputs,
VIN = 3.4 V
or GND
All 5.5 V 1, 2, 3 6.0
Outputs open 4/
OE1 = OE2 = GND
MR = VCC
S0 = S1 = VCC
DS0 = DS7 = GND
fCP= 10 MHz
50% duty cycle
Eight bits toggling
fi = 2.5 MHz
50% duty cycle
For nonswitching inputs
VIN = VCC or GND
For switching
inputs,
VIN = VCC or
GND
All 5.5 V 1, 2, 3 7.8
For switching
inputs,
VIN = 3.4 V
or GND
All 5.5 V 1, 2, 3 16.8
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92216
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 8
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s - Continued.
Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/
-55C TC +125C
+4.5 V VCC +5.5 V
unless otherwise specified
Device
type VCC Group A
subgroups Limits 3/ Unit
Min Max
Low level ground
bounce noise VOLP
7/ 13/ VIH = 3.0 V
VIL = 0.0 V
TA = +25C
See figure 4
See 4.4.1b
01, 03,
05 5.0 V 4 mV
02, 04,
06 1850
VOLV
7/ 13/ 01, 03,
05 5.0 V 4 mV
02, 04,
06 -1700
Functional tests 14/ VIH = 2.0 V, VIL = 0.8 V
Verify output VO
See 4.4.1d
All 4.5 V 7, 8 L H
All 5.5 V 7, 8 L H
Propagation delay time,
clock to output,
CP to Q0 or Q7
3003
tPLH,
tPHL
15/
CL = 50 pF minimum
RL = 500
See figure 5
01, 02 4.5 V 9, 10, 11 2.0 14.0 ns
03, 04 9, 10, 11 2.0 9.5
05, 06 9, 10, 11 2.0 7.5
Propagation delay time,
clock to output
CP to I/On
3003
tPHL,
tPLH
15/
01, 02 4.5 V 9, 10, 11 2.0 12.0 ns
03, 04 9, 10, 11 2.0 9.5
05, 06 9, 10, 11 2.0 7.5
Propagation delay
time, reset to output
MR to Q0 or Q7
3003
tPHL
15/ 01, 02 4.5 V 9, 10, 11 2.0 10.5 ns
03, 04 9, 10, 11 2.0 9.5
05, 06 9, 10, 11 2.0 7.5
Propagation delay
time, reset to output
MR to I/On
3003
tPHL
15/ 01, 02 4.5 V 9, 10, 11 2.0 15.0 ns
03, 04 9, 10, 11 2.0 11.5
05, 06 9, 10, 11 2.0 7.5
Propagation delay
time, output enable
OEn to I/On
3003
tPZH
tPZL
15/
01, 02 4.5 V 9, 10, 11 1.5 15.0 ns
03, 04 9, 10, 11 1.5 7.5
05, 06 9, 10, 11 1.5 7.5
Propagation delay
time, output disable
OEn to I/On
3003
tPHZ
tPLZ
15/
01, 02 4.5 V 9, 10, 11 1.5 9.0 ns
03, 04 9, 10, 11 1.5 6.5
05, 06 9, 10, 11 1.5 6.5
Setup time, select
high or low to clock,
S0 or S1 to CP
ts
15/ 01, 02 4.5 V 9, 10, 11 7.5 ns
03, 04 9, 10, 11 4.0
05, 06 9, 10, 11 4.0
Setup time, select
high or low I/On,
DS0 or DS7 to CP
ts
15/ 01, 02 4.5 V 9, 10, 11 5.5 ns
03, 04 9, 10, 11 4.5
05, 06 9, 10, 11 4.5
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92216
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 9
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s - Continued.
Test and
MIL-STD-883
test method 1/
Symbol Test conditions 2/
-55C TC +125C
+4.5 V VCC +5.5 V
unless otherwise specified
Device
type VCC Group A
subgroups Limits 3/ Unit
Min Max
Hold time, select
high and low,
S0 or S1 from CP
th
15/ CL = 50 pF minimum
RL = 500
See figure 5
01, 02 4.5 V 9, 10, 11 1.0 ns
03, 04 9, 10, 11 1.0
05, 06 9, 10, 11 1.0
Hold time, data high
or low I/On,
DS0 or DS7 from
CP
th
15/ 01, 02 4.5 V 9, 10, 11 1.5 ns
03, 04 9, 10, 11 1.5
05, 06 9, 10, 11 1.5
Clock pulse width,
CP high and low tw
15/ 01, 02 4.5 V 9, 10, 11 7.0 ns
03, 04 9, 10, 11 6.0
05, 06 9, 10, 11 6.0
Reset pulse width,
MR low tw
15/ 01, 02 4.5 V 9, 10, 11 7.0 ns
03, 04 9, 10, 11 6.0
05, 06 9, 10, 11 6.0
Recovery time,
MR high to CP trec
15/ 01, 02 4.5 V 9, 10, 11 7.0 ns
03, 04 9, 10, 11 6.0
05, 06 9, 10, 11 6.0
1/ For tests not listed in the referenced MIL-STD-883 (e.g. ICC), utilize the general test procedure of 883 under the conditions
listed herein.
2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I
herein. Output terminals not designated sha ll be high level logic, low level logic, or open, exc ept for all ICC and ICC tests,
the output terminals shall be open. When performing these tests, the current meter shall be placed in the circuit such that
all current flows through the meter.
3/ For negative and positive voltage and current values, the si gn designates the potential difference in reference to GND and
the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relat ive to the minimum
and maximum limits, as applicabl e, listed herein. All devices shall meet or exceed the limi ts specified in table I at
4.5 V VCC 5.5 V.
4/ This parameter is guaranteed, if not tested, to the limits specified in table I.
5/ Three-state output conditions required.
6/ This test may be performed ucing VIH = 3.0 V, but is guaranteed for VIH = 2.0 V.
7/ This test is required only for group A testin g, see 4.4.1 herein.
8/ Not more than one output should be shorted at a time. The duration of the short circuit test should not exceed one second.
9/ ICCD may be verified by the following equation:
ICCT - ICC - DHNTICC
I
CCD = ─────────────────────
fCP/2 + fiNi
where ICCT, ICC (ICCL or ICCH in table I), and ICC shall be the measur ed values of these parameters, for the device under test,
when tested as described in table I, herein. The values for DH, NT, fCP, fi, and Ni shall be as listed in the test conditions
column for ICCT in table I, herein.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
5962-92216
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
C SHEET 10
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristi c s - Continued.
10/ This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at
V
IN = VCC - 2.1 V (alternate method). Classes Q and V shall use the preferred method. When the test is performed using
the alternate test method, the maximum limit is equal to the number of inputs at a high TTL input level times 2.0 mA; and the
preferred method and limits are guaranteed.
11/ ICCT is calculated as follo ws:
I
CCT = ICC + DHNTICC + ICCD(fCP/2 + fiNi)
where:
I
CC = Quiescent supply curren t (any ICCL or ICCH)
D
H = Duty cycle for TTL inputs at 3.4 V
N
T = Number of TTL inputs at 3.4 V
ICC = Quiescent supply current delta, TTL inputs at 3.4 V
I
CCD = Dynamic power supply current caused by an input transition pair (HLH or LHL)
f
CP = Clock frequency for registered devices (fCP = 0 for nonregistered devices)
f
i = input frequency
N
i = Number of inputs at fi
12/ For ICC test in an ATE environment, the effect of parasitic output capacitive loadin g from the test environment must be taken
into account, as its effect is not intended to be included in the test results. The impact must be characterized and
appropriate offset factors must be applied to the test result.
13/ This test is for qualification only. Ground and VCC bounce t ests are performed on a non-s witching (qu ie scent) output and
are used to measure the magnitude of induced noise caused by other simultaneously switching outputs. The test is
performed on a low noise bench test fixture. For the device under test, all outputs shall be loaded with 500 of load
resistance and a minimum of 50 pF of loa d capacitance (see figure 4). Only chip capacitors and resistors shall be used.
The output load components shall be located as close as possible to the device outputs. It is suggested, that whenever
possible, this distance be kept to less than 0.25 inches. Decoupling capacitors shall be placed in parallel from VCC to
ground. The values of these decoupling capacitors shall be determined b y the device manufacturer. The low and high level
ground and VCC bounce noise is measure d at the quiet output using a 1 GHz minimum bandwidth oscilloscope with a 50
input impedance.
The device in puts shall be conditioned such that all outputs are at a high nominal VOH level. The device inputs shall then be
conditioned such that they switch simultaneously and the output under test remains at VOH as all other outputs possible are
switched from VOH to VOL. VOHV and VOHP are then measured from the nominal VOH level to the largest negative and positive
peaks, respectively (see figure 4).
For device types 01, 03, and 05, were never made available by an approved source of supply.
14/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic
patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of each
input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table
in figure 2 herein. Functiona l tests shall be performed in sequence as approved by the qualifying activity on qualified
devices. For outputs, L < 1.5 V, H 1.5 V.
15/ AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. Minimum
propagation delay time limits for VCC = 4.5 V and 5.5 V are guaranteed, if not tested, to the limits specified in table I, herein.
For propagation delay tests, all paths must be tested.
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DSCC FORM 2234
APR 97
Device types All
Case outlines R, S and 2
Terminal
number Terminal symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
S0
OE1
OE2
I/O6
I/O4
I/O2
I/O0
Q0
MR
GND
DS0
CP
I/O1
I/O3
I/O5
I/O7
Q7
DS7
S1
VCC
Terminal descriptions
Terminal symbol Description
CP Synchronous timing input
DS0 Serial data input for right shift
DS7 Serial data input for left shift
S0, S1 Mode select synchronous control inp uts
MR Asynchronous master reset control input (active low)
OE1, OE2 Three-state output enable inputs (active low)
I/On ( n = 0 to 7) Parallel data inputs or three-state parallel outputs
Q0 to Q7 Serial outputs
FIGURE 1. Terminal connections.
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Asynchronous operations (CP, DS0, DS7 = X; OE1, OE2 = L; S0 and S1 shall not simultaneously = H)
Mode Inputs Input/outputs Outputs
MR S0 S1 I/O0 I/O1 1/O7 Q0 Q7
Reset L X X L L L L L
Hold H L L N/C N/C N/C N/C N/C
Synchronous operation (MR = H; OE1, OE2 = L)
Mode Inputs Inputs/outputs 1/ 2/ 3/ Outputs 2/
CP S0 S1 DS0 DS7 I/O0 I/O1 I/O7 Q0 Q7
Load H H X X Z Z Z D0 D7
Shift right L H L X L D0 D6 L D6
Shift right L H H X H D0 D6 H D6
Shift left H L X L D1 D2 L D1 L
Shift left H L X H D1 D2 H D1 H
Mode Inputs Inputs/outputs 1/ Outputs
OE1 OE2 I/O0 I/O1 I/O7 Q0 Q7
High impedance H X Z Z Z 4/ 4/
X H Z Z Z 4/ 4/
1/ When S0 = S1 = H simultaneously, outputs I/On are in high impedance state (Z). This is an asynchronous operation.
2/ Shown in the state of the outputs after the low-to-hig h transition of CP. D0 to D7 represent the data that was
stored in the eight flip flops, Q0 to Q7, after the clock transition.
3
/ In the load mode, the I/On pins act as data inputs to the register. External data input to these pins will be entered
into the register on the low-to-high transition of the clock.
4
/ During the high impedance condition, shift, hold, load, and reset operations can still occur. Outputs Q0 and Q7 are
effected accordingly.
H = High voltage lev el
L = Low voltage level
X = Don't care
= Low-to-high CP transition
Z = High impe dance
N/C = No change
FIGURE 2. Truth tables.
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FIGURE 3. Logic diagram.
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NOTES:
1. CL includes a 47 pF chip capacitor (-0 percen t, +20 percent) and at least 3 pF of equivalent capacitance from the test jig
and probe.
2. RL = 450 1 percent, chip resistor in series with a 50 termination. For monitored outputs, the 50 termination shall
be the 50 characteristic impeda nce of the coaxial connector to the oscilloscope.
3. Input signal to the device under test:
a. VIN = 0.0 V to 3.0 V; duty cycle = 50 percent; fIN 1 MHz.
b. tr, tf = 3.0 ns 1.0 ns. For input signal generators incapable of maintaining these values of tr and tf, the 3.0 ns limit
may be increased up to 10 ns, as needed, m aintaining the 1.0 ns tolerance and guaranteein g the results at 3.0 ns
1.0 ns; skew between any two switching inputs signals (tsk) 250 ps.
FIGURE 4. Ground bounce waveforms and test circuit.
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FIGURE 5. Switching waveforms and test circuit.
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NOTES:
1. When measuring tPLZ and tPZL: VTEST = 7.0 V.
2. When measuring tPHZ, tPZH, tPLH, and tPHL: VTEST = Open.
3. The tPZL and tPLZ reference waveform is for the output under test with internal conditions such that the output is low at
VOL except when disabled by the output enable control. The tPZH and tPHZ reference waveform is for the output under
test with internal conditions such that the output is high at VOH except when disabled by the outp ut enable control.
4. CL = 50 pF minimum or equivalent (includ es test jig an d probe capacitance).
5. RT = 50 or equivalent.
6. RL = 500 or equivalent.
7. Input signal from pulse generator: VIN = 0.0 V to 3.0 V; PRR 10 MHz; tr 2.5 ns; tf 2.5 ns; tr and tf shall be
measured from 0.3 V to 2.7 V and from 2.7 V to 0.3 V respectively; duty cycle = 50 percent.
8. Timing parameters shall be tested at a minimum input frequency of 1 MHz.
9. The outputs are measured one at a time with one transition per measurement.
FIGURE 5. Switching waveforms and test circuit – Continued.
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4. VERIFICATION
4.1 Sampling and i nspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. F or device cla sses Q and V, screening shall be in accorda nce with MIL-PRF-38535, and shall be conduc ted
on all devices prior to qualific ation and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document re vision
level control and shall be ma de available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicabl e, in accordanc e with the intent specified in
method 1015.
(2) TA = +125C, minimum.
b. Interim and final electrical test parameters shall be as specified in table II herein.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained unde r
document revision level contro l of the device manufacturer's Technology Review Board (TRB) in accorda nce with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicabl e, in accordanc e with the intent specified in
method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table II herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-3853 5, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification ins pection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspectio ns to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordanc e with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in acc ordance with MIL-PRF-38535, appendix A and as specified here in. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 an d herein for groups A, B, C, D, and E inspectio ns
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. Ground and VCC bounce tests are required for all device classes. These tests shall be p erformed only for initial
qualification, after process or design changes which may affect the performance of the device, and any changes to the
test fixture. VOLP, VOLV, VOHP, and VOHV shall be meas ured for the worst case outputs of the device. All other outputs
shall be guaranteed, if not tested, to the limits established f or the worst case outputs. The worst case outputs tested
are to be determined by the manufacturer. T est 5 devices assembled i n the worst case package type supplied to this
document. All other package t ypes shall be guaranteed, if not tested, to the limits established for the worst case
package. The package type t o be tested sh all be determined by the manufacturer. The device manuf acturer will
submit to DSCC-VA data that shall include all measured peak values for each device tested and detailed oscilloscope
plots for each VOLP, VOLV, VOHP, and VOHV from one sample part per function. The plot shall contain the waveforms of
both a switching output and the output under test.
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Each device manufacturer shall test product on the fixtures they currently use. When a new fixture is used, the device
manufacturer shall inform DSCC-VA of this change and test the 5 devices on both the new and old test fixtures. The
device manufacturer shal l then submit to DSCC-VA data from testing on both fixtures that shall include all measured
peak values for each device tested and detailed oscilloscop e plots for each VOLP, VOLV, VOHP, and VOHV from one
sample part per function. The plot shall contain the waveforms of both a switching output and the output under test.
c. CIN and COUT shall be measur ed only for initial qualification and after process or design changes which may affect
capacitance. CIN and COUT shall be measured between the designated termina l and GND at a frequency of 1 MHz.
For CIN and COUT, test all applicable pins on five devices with zero failures.
d. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table in figure 2 herein. The test
vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All possible input
to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein. For device
classes Q and V, subgroups 7 and 8 shall i nclude verifying the functionalit y of the device.
TABLE II. Electrical test requirements.
Test requirements Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
class M Device
class Q Device
class V
Interim electrical
parameters (see 4.2) - - - 1 1
Final electrical
parameters (see 4.2) 1/ 1, 2, 3, 4, 7, 8, 9,
10, 11 1/ 1, 2, 3, 4, 7,
8, 9, 10, 11 2/ 1, 2, 3, 4, 7,
8, 9, 10, 11
Group A test
requirements (see 4.4) 1, 2, 3, 4, 5, 8, 9, 10,
11 1, 2, 3, 4, 7, 8, 9,
10, 11 1, 2, 3, 4, 7, 8, 9,
10, 11
Group C end-point electrical
parameters (see 4.4) 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 7, 8, 9,
10, 11
Group D end-point electrical
parameters (see 4.4) 1, 2, 3 1, 2, 3 1, 2, 3
Group E end-point electrical
parameters (see 4.4) 1, 7, 9 1, 7, 9 1, 7, 9
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1 and 7.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b. TA = +125C, minimum.
c. Test duration: 1,000 hours, except as permitted b y method 1005 of MIL-STD-883.
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DSCC FORM 2234
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4.4.2.2 Additional criteria for device classes Q and V. The steady-state lif e te st duration, test condition and test temperature,
or approved alternativ es shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under docum ent revision level control by the device manufa c turer' s TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein.
4.4.4 Group E inspection. Group E inspection is required onl y for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a. End-point electrical parameters shall be as specifi ed in table II herein.
b. For device classes Q and V, the devices or test vehicle shall be subject ed to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF - 38535, appendi x A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25C 5C,
after exposure, to the subgrou ps specified in table II herein.
5. PACKAGING
5.1 Packaging requirements. The requir eme nts for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming t o this drawing are intended for use for Government microcircuit application s
(original equipment), desig n applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device cover ed by a contractor-
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed chan ges to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished usin g DD Form 1692, Engineering Cha nge Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephon e
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, s ymbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-133 1.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of suppl y for device classes Q and V are listed in QML- 38535.
The vendors listed in QML-38535 h ave su bmitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for cla ss M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 h ave agreed to this drawing and a certificate of compliance (se e 3.6 herein) has been
submitted to and accepted by DSCC-VA.
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 10-04-19
Approved sources of suppl y for SMD 5962-92216 are listed below for immediate acq uisition information only and
shall be added to MIL-HDBK-103 an d QML-38535 during the ne xt revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been subm itted to and accepted by DSCC-VA. This information bulletin is superseded
by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current
sources of supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9221601M2A 3/ 54FCT299T
5962-9221601MRA 3/ 54FCT299T
5962-9221602M2A 0C7V7 IDT54FCT299TLB
5962-9221602MRA 0C7V7 IDT54FCT299TDB
5962-9221602MSA 0C7V7 IDT54FCT299TEB
5962-9221603M2A 3/ 54FCT299AT
5962-9221603MRA 3/ 54FCT299AT
5962-9221604M2A 0C7V7 IDT54FCT299ATLB
5962-9221604MRA 0C7V7 IDT54FCT299ATDB
5962-9221604MSA 0C7V7 IDT54FCT299ATEB
5962-9221605M2A 3/ 54FCT299CT
5962-9221605MRA 3/ 54FCT299CT
5962-9221606M2A 0C7V7 IDT54FCT299CTLB
5962-9221606MRA 0C7V7 IDT54FCT299CTDB
5962-9221604MSA 0C7V7 IDT54FCT299CTEB
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number m ay not
satisfy the performance requirements of this drawing.
3/ Not available from an approved source of supply.
Vendor CAGE Vendor name
number and address
0C7V7 QP Semiconductor
2945 Oakmead Village Court
Santa Clara, CA 95051
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoeve r for any inaccuracies in the
information bulletin.
