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FEATURES
DESCRIPTION/ORDERING INFORMATION
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NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
NC − No internal connection
SN74ALVCF1628353.3-V CMOS 18-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
SCES397A – JULY 2002 – REVISED AUGUST 2004
•Member of the Texas Instruments Widebus™Family
•Ideal for Use in PC133 Register DIMM•Typical Output Skew . . . <250 ps•V
CC
= 3.3 V ±0.3 V . . . Normal Range•V
CC
= 2.7 V to 3.6 V . . . Extended Range•V
CC
= 2.5 V ±0.2 V•Rail-to-Rail Output Swing for Increased NoiseMargin
•Balanced Output Drivers . . . ±18 mA•Low Switching Noise•Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II•ESD Protection Exceeds JESD 22- 2000-V Human-Body Model (A114-A)- 200-V Machine Model (A115-A)- 1000-V Charged-Device Model (C101)
This 18-bit universal bus driver is designed for 2.3-Vto 3.6-V V
CC
operation.
Data flow from A to Y is controlled by theoutput-enable (OE) input. The device operates in thetransparent mode when the latch-enable (LE) input ishigh. When LE is low, the A data is latched if theclock (CLK) input is held at a high or low logic level. IfLE is low, the A data is stored in the latch/flip-flop onthe low-to-high transition of CLK. When OE is high,the outputs are in the high-impedance state.
The SN74ALVCF162835 has series dampingresistors in the device output structure that reduceswitching noise in 128-MB and 256-MB SDRAMmodules. Designed with a drive capability of ±18 mA,this device is a midway drive between theSN74ALVC162835 (±12 mA) and SN74ALVC16835(±24 mA).
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Tube SN74ALVCF162835DLSSOP - DL ALVCF162835Tape and reel SN74ALVCF162835DLR-40°C to 85°C
TSSOP - DGG Tape and reel SN74ALVCF162835GR ALVCF162835TVSOP - DGV Tape and reel SN74ALVCF162835VR VF2835
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2002–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
OE
CLK
Y1
1D
C1
CLK
To 17 Other Channels
LE
A1
27
30
28
54
3
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
SCES397A – JULY 2002 – REVISED AUGUST 2004
The SN74ALVCF162835 is a faster version of the SN74ALVC162835. It is suitable for PC133 applications and,particularly, SDRAM modules clocked at 133 MHz.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullupresistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
OUTPUT
YOE LE CLK A
H X X X ZL H X L LL H X H HL L ↑L LL L ↑H HL L L or H X Y
0
(1)
(1) Output level before the indicated steady-state input conditions wereestablished
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
(1)
SN74ALVCF1628353.3-V CMOS 18-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
SCES397A – JULY 2002 – REVISED AUGUST 2004
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range -0.5 4.6 VV
I
Input voltage range
(2)
-0.5 4.6 VV
O
Output voltage range
(2) (3)
-0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 or V
I
< V
CC
-50 mAI
OK
Output clamp current V
O
< 0 -50 mAI
O
Continuous output current ±50 mAContinuous current through each V
CC
or GND ±100 mADGG package 64θ
JA
Package thermal impedance
(4)
DGV package 48 °C/WDL package 56T
stg
Storage temperature range -65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) This value is limited to 4.6 V maximum.(4) The package thermal impedance is calculated in accordance with JESD 51-7.
MIN MAX UNIT
V
CC
Supply voltage 2.3 3.6 VV
CC
= 2.3 V to 2.7 V 1.7V
IH
High-level input voltage VV
CC
= 2.7 V to 3.6 V 2V
CC
= 2.3 V to 2.7 V 0.7V
IL
Low-level input voltage VV
CC
= 2.7 V to 3.6 V 0.8V
I
Input voltage 0 V
CC
VV
O
Output voltage 0 V
CC
V-6V
CC
= 2.3 V
-8
-6I
OH
High-level output current V
CC
= 2.7 V mA-12
-8V
CC
= 3 V
-18
6V
CC
= 2.3 V
8
6I
OL
Low-level output current V
CC
= 2.7 V mA12
8V
CC
= 3 V
18∆t/∆v Input transition rise or fall rate 10 ns/VT
A
Operating free-air temperature -40 85 °C
(1) All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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ELECTRICAL CHARACTERISTICS
TIMING REQUIREMENTS
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
SCES397A – JULY 2002 – REVISED AUGUST 2004
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
I
OH
= -0.1 mA 2.3 V to 3.6 V V
CC
- 0.2I
OH
= -6 mA 1.92.3 VI
OH
= -8 mA 1.7V
OH
I
OH
= -6 mA 2.2 V2.7 VI
OH
= -12 mA 2I
OH
= -8 mA 2.43 VI
OH
= -18 mA 2I
OL
= 0.1 mA 2.3 V to 3.6 V 0.2I
OL
= 6 mA 0.42.3 VI
OL
= 8 mA 0.55V
OL
I
OL
= 6 mA 0.4 V2.7 VI
OL
= 12 mA 0.6I
OL
= 8 mA 0.553 VI
OL
= 18 mA 0.8V
IK
V
CC
= 2.3 V, I
I
= -18 mA 3.6 V -1.2 VV
hys
V
CC
= 3.6 V 3.6 V 100 mVI
I
V
I
= V
CC
or GND 3.6 V ±5µAI
OZ
V
O
= V
CC
or GND 3.6 V ±10 µAI
CC
V
I
= V
CC
or GND, I
O
= 0 3.6 V 0.1 40 µA∆I
CC
One input at V
CC
- 0.6 V, Other inputs at V
CC
or GND 3 V to 3.6 V 750 µAC
i
Inputs V
I
= 0 V 3.3 V 3.5 pFC
o
Outputs V
O
= 0 V 3.3 V 4.5 pF
(1) All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 and Figure 2)
V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 2.7 V±0.2 V ±0.3 V
UNITMIN MAX MIN MAX MIN MAX
f
clock
Clock frequency 150 150 150 MHzLE high 3.3 3.3 3.3t
w
Pulse duration nsCLK high or low 3.3 3.3 3.3Data before CLK↑1.8 1.5 1t
su
Setup time CLK high 1.9 1.6 1.5 nsData before LE↓
CLK low 1.3 1.1 1Data after CLK↑0.6 0.6 0.6t
h
Hold time nsData after LE↓CLK high or low 1.4 1.7 1.4
4
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SWITCHING CHARACTERISTICS
SWITCHING CHARACTERISTICS
OPERATING CHARACTERISTICS
SN74ALVCF1628353.3-V CMOS 18-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
SCES397A – JULY 2002 – REVISED AUGUST 2004
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 and Figure 2)
V
CC
= 2.5 V V
CC
= 3.3 VV
CC
= 2.7 VFROM TO
±0.2 V ±0.3 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX MIN MAX MIN MAX
f
max
150 150 150 MHzA 1 4 4.6 1 3.5t
pd
LE Y 1.3 5.5 5.4 1.3 4.6 nsCLK 1.4 5.9 5.6 1.4 3.5t
en
OE Y 1.4 5.9 6 1.1 5 nst
dis
OE Y 1 4.7 4.6 1.3 4.2 nst
sk(o)
500 ps
from 0°C to 65°C, C
L
= 50 pF
V
CC
= 3.3 VFROM TO
±0.15 VPARAMETER UNIT(INPUT) (OUTPUT)
MIN MAX
t
pd
CLK Y 1.8 3.5 ns
T
A
= 25°C
V
CC
= 2.5 V V
CC
= 3.3 VPARAMETER TEST CONDITIONS UNITTYP TYP
Outputs enabled 27 33C
pd
Power dissipation capacitance C
L
= 0 pF, f = 10 MHz pFOutputs disabled 16 21
5
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PARAMETER MEASUREMENT INFORMATION
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH − 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PULSE DURATION
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
SN74ALVCF162835
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
SCES397A – JULY 2002 – REVISED AUGUST 2004
V
CC
= 2.5 V ±0.2 V
Figure 1. Load Circuit and Voltage Waveforms
6
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PARAMETER MEASUREMENT INFORMATION
VOH
VOL
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 6 V
Open
GND
500 Ω
500 Ω
tPLH tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
1.5 V 1.5 V 2.7 V
0 V
1.5 V 1.5 V VOH
VOL
0 V
1.5 V VOL + 0.3 V
1.5 V VOH − 0.3 V
0 V
1.5 V 2.7 V
0 V
0 V
2.7 V
0 V
Input
2.7 V 2.7 V
3 V
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WA VEFORMS
PULSE DURATION
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
1.5 V 1.5 V
tw
th
tsu
1.5 V 1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
SN74ALVCF1628353.3-V CMOS 18-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
SCES397A – JULY 2002 – REVISED AUGUST 2004
V
CC
= 2.7 V AND 3.3 V ±0.3 V
Figure 2. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
74ALVCF162835DLG4 ACTIVE SSOP DL 56 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
74ALVCF162835GRE4 ACTIVE TSSOP DGG 56 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
74ALVCF162835GRG4 ACTIVE TSSOP DGG 56 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
74ALVCF162835VRE4 ACTIVE TVSOP DGV 56 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
74ALVCF162835VRG4 ACTIVE TVSOP DGV 56 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
SN74ALVCF162835DL ACTIVE SSOP DL 56 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples
SN74ALVCF162835GR ACTIVE TSSOP DGG 56 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
SN74ALVCF162835VR ACTIVE TVSOP DGV 56 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor
or Sales Office
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 28-Aug-2010
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74ALVCF162835GR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1
SN74ALVCF162835VR TVSOP DGV 56 2000 330.0 24.4 6.8 11.7 1.6 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74ALVCF162835GR TSSOP DGG 56 2000 367.0 367.0 45.0
SN74ALVCF162835VR TVSOP DGV 56 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
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