GP2021/IG/GQ1N - Zarlink Semiconductor, Inc.

Features

• 12 Fully Independent Correlation Channels

GPS

12-CHANNEL

CORRELATOR

POWER AND

RESET

CONTROL

MICRO_CLK

NRESET_O/PA<22:20> ARM60

INTERFACE

MEMORY

INTERFACE

ARM SYSTEM

ALE_I/PNCS WREN READ

STANDARD INTERFACE

MICROPROCESSOR INTERFACE

DUAL UART REAL TIME CLOCK

WRPROG

NINTEL/ MOT

A<9:0>

NARMSYS

D<15:0>

SIGN, MAG

SAMPCLK

CLK_T, CLK_I

POWER_GOOD

PLL_LOCK

NRESET_I/P

ACCUM_INT MEAS_INT RXA RXB XIN XOUTTXA TXB

DATA BUS

CONTROL BUS

Ordering Information

GP2021/IG/GQ1N (Trays)

GP2021/IG/GQ1Q (Tape and Reel)

• On-Chip Dual UART and Real Time Clock

• Compatible with most 16- and 32-bit Microprocessors

• Memory Control Logic for ARM60 Microprocessor

• Low Voltage, Low Current Power-Down Mode

• Power Dissipation 150mW Typical

• Compatible with GP2015 and GP2010 RF Front Ends

• Battery Backup Voltage 2.2V (min)

Applications

•GPS Navigation Systems

•GPS Geodetic Receivers

•Time Transfer Receivers

Related Global Positioning Products

Description

The GP2021 is a 12-channel C/A code baseband correlator

for use in NAVSTAR GPS satellite navigation receivers.

The GP2021 complements the GP2015 and GP2010 C/A

code RF downconverters available from Zarlink

Semiconductor.

The GP2021 is compatible with most 16-bit and 32-bit

microprocessors, especially those from Motorola and Intel,

with additional on-chip support for the ARM60 32-bit RISC

processor. When the ARM60 is used, the on-chip memory

management functions allow implementation of a full GPS

receiver with minimal external logic.

The GP2021 allows individual channel de-activation, for

systems not requiring full 12-channel operation, to save

power and processor loading. Receiver power may be

further conserved by reducing the supply voltage to 2.2V

under battery backup; all system functions are then

disabled but the 32.768kHz oscillator and Real Time Clock

are maintained for the microprocessor to estimate satellite

visibility at power-on to reduce signal acquisition time.

DS4077 Issue 3.2 April 2001

GP2021

GPS 12-Channel Correlator

Description

GPS receiver RF front end

(48-lead TQFP package)

GPS receiver RF front end

(44-lead PQFP package)

Data ref.

DS4374

DS4056

Part

GP2015

GP2010

32 bit RISC microprocessor DS3553P60ARM-B

App. Note GPS ORION 12 Channel

GPS Receiver Reference

Design

AN4808

App. Note GPS2000 GPS Receiver

Hardware Design

AN4855

GP2021

NRD/NC

ARM_ALE/NC

DBE/NC

ACCUM_INT

MEAS_INT

NBW/WRPROG

NMREQ/DISCIP2

NOPC/NINTELMOT

NRW/DISCIP3

MCLK/NC

ABORT MICRO_CLK

DISCIO

A22/READ

VDD

VSS

A21/NCS

A20/WREN

Description

MULTI_FN_IO

POWER _GOOD

NRESET_OP

NARMSYS

XIN

XOUT

TXA

TXB

RXA

RXB

NROM/NC

NEEPROM/NC

NSPARE_CS/NC

VDD

VSS

NRAM/NC

NW0/NC

NW1/NC

NW2/NC

NW3/NC

Description Pin

Description

A1/ALE_IP

A0/NRESET_IP

VDD

VSS

D10

Description

D11

D12

D13

D14

D15

PLL_LOCK

VDD

DISCOP

VSS

CLK_T

CLK_I

VSS

SAMPCLK

VDD

NBRAM / DISCIP4

SIGN0

MAG0

SIGN1

MAG1

DISCIP1

Table 1 Pin assignments

Figure 2 Pin connections - top view

120

60 41

PIN 1 IDENT

GP2021

GQ80

Absolute Maximum Ratings

These are not the operating conditions, but are the absolute

limits which if exceeded, even momentarily, may cause

permanent damage. To ensure sustained correct operation

the device should be used within the limits given under

Electrical Characteristics. It is essential for both VDD and

VSS to be present before input signals are applied.

Page

CONTENTS

TYPICAL GPS RECEIVER

PIN DESCRIPTION

FUNCTIONAL DESCRIPTION

12-Channel Correlator

Tracking Modules

PERIPHERAL FUNCTIONS

Dual UART

Real Time Clock (RTC) and Watchdog

Power and Reset Control

Discrete l/O

Digital System Test Interface

MICROPROCESSOR INTERFACE

SOFTWARE REQUIREMENTS

CONTROLLING THE GP2021

DETAILED DESCRIPTION OF REGISTERS

GP2021 Register Map

Correlator Registers

Tracking Channel Registers

Peripheral Functions Registers

Real Time Clock and Watchdog

DUART

SYSTEM CONTROL

GENERAL CONTROL

ELECTRICAL CHARACTERISTICS

TIMING CHARACTERISTICS

Supply voltage (VDD)

Input voltage (any input pin)

Output voltage (any output pin)

Storage temperature

VSS20·3V to 16V

VSS20·3V to VDD10·3V

255°C to 1150°C

GP2021

TYPICAL GPS RECEIVER

Fig. 3 shows a typical GPS receiver employing a GP2010

or GP2015 RF front end, a GP2021 correlator and an

ARM60 32-bit RISC microprocessor.

A single front end may be used, since all GPS satellites

use the same L1 frequency of 1575·42 MHz. However, in

order to achieve better sky coverage, it is sometimes

desirable to use more than one antenna. In this case,

separate front ends will be required.

The RF section, GP2010 or GP2015, performs down

conversion of the L1 signal for digital baseband processing.

The resultant signal is then correlated in the GP2021 with

an internally generated replica of the satellite code to be

received. Individual codes for each channel may be

selected independently to enable acquisition and tracking

of up to 12 different satellites simultaneously. The results

of the correlations form the accumulated data and are

transferred to the microprocessor to give the broadcast

satellite data (the Navigation Message) and to control the

software signal tracking loops.

The GP2021 can be interfaced to one of two styles of front

end. In Real_lnput mode, the front end supplies either

a 1-bit (sign) or 2-bit (sign and magnitude) signal to either

the SIGN0/MAG0 or SIGN1/MAG1 inputs of the GP2021.

Alternatively, in Real_lnput mode, two separate front ends

can be connected to a single GP2021 and selected under

software control. The GP2015 and GP2010 are Real_lnput

mode front ends.

In Complex_lnput mode, the front end is required to supply

In-phase (I) and Quadrature (Q) signals to the SIGN0/

MAG0 and SIGN1/MAG1 inputs respectively. Hence, only

a single front end can be used with each GP2021 in

Complex_lnput mode. See Table 3, page 6.

Figure 3 Block diagram of a typical ARM-based receiver

GP2010/

GP2015

10MHz

TCXO

12-CHANNEL

CORRELATOR

SIGN

MAG

SAMPCLK

CLK_T

CLK_I

PLL_LOCK

L1 ANTENNA

WREN

READ

MICRO_CLK

PERIPHERAL

FUNCTIONS

ACCUM_INT, MEAS_INT

CONTROL

DATA

ADDR

MEMORY CONTROL

MEMORY

ARM60

TX/RX

SERIAL COMMS PORT

GP2021

PIN DESCRIPTIONS

All VSS and VDD pins must be connected to their respective supplies in order to ensure reliable operation. Any unused

inputs must be tied high or low. Table 2 describes the pin functions in Real_lnput mode and assumes a master clock input

frequency of 40MHz. Those pins whose functions differ in Complex_lnput mode are described in Table 3.

Note that those pin names containing a forward slash (/) have dual functionality between ARM System and Standard

Interface modes. The pin mnemonic for ARM System mode always precedes the forward slash.

ARM system mode

15,35

56,69

14,34

55,67

VSS

VDD

MULTI_FN_IO

POWER _GOOD

NRESET_OP

NARMSYS

XIN

XOUT

TXA

TXB

RXA

RXB

NROM/NC

NEEPROM/NC

NSPARE_CS/NC

NRAM/NC

NW0/NC

NW1/NC

NW2/NC

NW3/NC

NRD/NC

ARM_ALE/NC

DBE/NC

Description

Pin Signal name Type Standard interface mode

Ground pins

Power supply to device

I/O

Multi-function input / output. Its function is configured by the IO_CONFIG register.

After a GP2021 reset it acts as the Digital System Test Enable input. It can also be

configured as a discrete output, or a discrete input if certain conditions are met.

Can be configured as the TRIGGER

input to the DEBUG block

ROM Chip Select output (active low).

EEPROM Chip Select output (active low)

Spare Chip Select output (active low).

RAM Chip Select output (active low).

Byte 0 Write Strobe output (active low).

Byte 1 Write Strobe output (active low).

Byte 2 Write Strobe output (active low).

Byte 3 Write Strobe output (active low).

Read Data Strobe output (active low).

ALE output to the microprocessor (active

high). Controls the transparent latches at

the microprocessor address outputs.

Data Bus Enable output to the

microprocessor. When Low, places the

microprocessor data bus drivers in a high

impedance state.

Power Monitor input. High for normal operation. Low forces the GP2021 into

Power Down mode.

System Reset output (active low). Lasts for 4 MICRO_CLK cycles after all reset

conditions have cleared.

Processor Mode Selection input. When low, this input selects ARM System mode.

When high, standard Interface mode is selected.

Crystal input connection to Real Time Clock.

Crystal output connection from Real Time Clock.

Transmit Data output from Channel A of the dual UART.

Transmit Data output from Channel B of the dual UART.

Receive Data input to Channel A of the dual UART. This pin acts as a master

clock input in Digital System Test mode.

Receive Data input to Channel B of the dual UART. This pin acts as the Real Time

Clock reset in Digital System Test mode.

Unused output (do not connect)

Unused output (do not connect).

Unused output (do not connect.)

Unused output (do not connect).

Table 2 Pin descriptions cont…

GP2021

ARM system mode

38-45

ACCUM_INT

MEAS_INT

NBW/WRPROG

NMREQ/DISCIP2

NOPC/NINTELMOT

NRW/DISCIP3

MCLK/NC

ABORT/MICRO_CLK

DISCIO

A22/READ

A21/NCS

A20/WREN

A<9:2>

A1/ALE_IP

A0/NRESET_IP

Description

Pin Signal name Type Standard interface mode

I/O

A free running interrupt to the microprocessor. It allows control of data transfer

between the accumulators in the correlator and the microprocessor. It is active

low when configured for ARM System mode or Motorola mode and is active high

in Intel mode.

An interrupt to the microprocessor. It allows control of measurement data transfer

between the correlator and the microprocessor. It is active Low when configured

for ARM System mode or Motorola mode and is active High in Intel mode.

Byte/Word input from the

microprocessor. Low indicates a byte

transfer, and high a word transfer.

Memory Request input from the

microprocessor. Low indicates that the

microprocessor requires a memory

access during the following cycle.

Opcode fetch input from the

microprocessor. Low indicates that an

instruction is being fetched and igh that

data is being transferred.

Read/Write Select input from the

microprocessor. Low indicates a read

cycle and high a write cycle.

Microprocessor Clock output (nominally

20MHz). Its phases can be stretched

under control of the Microprocessor

Interface.

Write-Read Program input. In Intel

mode, High selects 486 interface and

low 186 style. Unused in Motorola mode

Multi-purpose discrete input.

High selects Motorola mode and low

Intel mode.

Multi-purpose discrete input.

Unused output (do not connect).

Abort output to the microprocessor.

Generates a valid ARM Data Abort

sequence, triggered by a rising edge at

MULTI_FN_IO if this function is enabled.

20MHz Clock output. Provides a 20MHz

clock with a 1:1 mark-to-space ratio.

Multi-purpose discrete input/output. After a GP2021 reset it is configured as an

input.

Address input from the microprocessor.

A<22:20> are decoded to select the

address space partitioning.

Address input from the microprocessor.

A<22:20> are decoded to select the

address space partitioning.

Address input from the microprocessor

A<22:20> are decoded to select the

address space partitioning.

Read input from the microprocessor. In

Intel mode it is the active low read strobe.

In Motorola mode it is the Read (high)/

Write (low) select line.

GP2021 Chip Select input (active low).

Write-Read Strobe input from the

microprocessor. In Intel mode it is the

active low write strobe. In Motorola mode

it is the active high Write-Read strobe.

Address input 1 from the micro-

processor. A<1:0> are decoded to

provide individual byte write selection via

NW<3:0>.

Address input 0 from the micro-

processor. A<1:0> are decoded to

provide individual byte write selection via

NW<3:0>.

Address Inputs <9:2> from the microprocessor. These allow register selection.

Table 2 Pin descriptions (continued) cont…

Address Latch Enable input from

microprocessor (active high)

Reset input (active low).

GP2021

ARM system mode

48-54

57-65

D0<0:15>

PLL_LOCK

DISCOP

CLK_T

CLK_I

SAMPCLK

NBRAM / DISCIP4

SIGN0

MAG0

SIGN1

MAG1

DISCIP1

Description

Pin Signal name Type Standard interface mode

I/O

Bidirectional data bus.

PLL Lock Indicator input from RF section. When High this signal indicates that

the PLL within the RF section is in lock and the master clock inputs have stabilised.

Multi-purpose discrete output.

Master clock input (40MHz).

Inverted Master clock input.

Sample Clock output to the front end. Provides a 5.71 4MHz clock with a 4:3

mark-to-space ratio.

Battery backed RAM select input.

Defines the state of the NRAM output in

Power Down mode.

Multi-purpose discrete input.

SIGN0 input from the RF section.

MAG0 input from the RF section.

SIGN1 input from a second, optional, RF section.

MAG1 input from a second, optional, RFsection

Multi-purpose discrete input.

Table 2 Pin descriptions (continued)

Difference between Real and Complex_lnput Mode

The input mode is selected by the FRONT_END_MODE

bit in the SYSTEM_SETUP register. It defaults to

Real_lnput mode at power-up. The differences between

Real and Complex input mode are summarised in Table 3.

Recommended Master clock frequency

GP2021 internal clocking (Note 1)

MICRO_CLK 2 output

Frequency

Mark: space

Pin No 76

Pin No 77

Pin No 78

Pin No 79

Input Signal Sampling Rate

SAMPCLK output

Frequency

Mark: space

Real_lnput mode

40MHz

40MHz47

20MHz

1:1

SIGN0

MAG0

SIGN 1

MAG 1

5·714MHz

4:3

Complex_lnput mode

35MHz

35MHz46

17·5MHz

1:1

SIGN_I

MAG_I

SIGN_Q

MAG_Q

5·833MHz

Not available

(held Low)

Description

NOTES

1. The GP2021 interrupt and TIC timebase dividers are clocked by this resulting clock.

2. The MCLK output is derived from this signal. In ARM mode the phases of MCLK are stretched

by the Microprocessor Interface block.

Table 3

GP2021

FUNCTIONAL DESCRIPTION

The GP2021 incorporates a 12-Channel GPS Correlator,

together with microprocessor support functions including

a Dual UART, a Real Time Clock and Memory Control

Logic for the ARM60 microprocessor. It can be configured

for either ARM System mode or Standard Interface mode.

When in ARM System mode the Memory Control Logic

allows an ARM60 microprocessor to interface with the

Correlator, Real Time Clock, Dual UART and a variety of

memory devices (i.e. SRAM, EPROM, Flash and

EEPROM), without the need for external glue logic.

In Standard Interface mode the GP2021 allows most 16-

and 32-bit microprocessors to interface with the Correlator,

Real Time Clock and Dual UART. More specifically, this

mode allows the interface to be configured for either Intel

or Motorola style microprocessor interfaces.

In the functional description which follows the correlator is

described first, followed by the peripheral functions.

12-Channel Correlator

Fig. 4 shows a block diagram of the correlator. It consists

of the following blocks:

Clock Generator

The Clock Generator block divides the frequency of the

master clock CLK_T/CLK_I by 6 or 7 to give the internal

multi-phase set of clocks. When in Real_lnput mode

CLK_T/CLK_I will normally be a 40MHz clock, which is

divided by 7. When in Complex_lnput mode it will normally

be at 35MHz which is divided by 6. The SAMPCLK pin is

an output giving a 4:3 mark-to-space ratio clock at

40 MHz 47 (= 5·714MHz) in Real_lnput Mode.

The Clock Generator also produces the MICRO_CLK

signal at half the master clock frequency (20 MHz for

Real_lnput mode, 17·5 MHz for Complex_lnput mode) with

a 1:1 mark-to-space ratio. This signal is output on the

MICRO_CLK pin in Standard Interface mode. However,

its main purpose is that of a synchronising clock to the

memory control logic in ARM System Mode and it is from

this that the processor clock output, MCLK, is derived.

MULTIPHASE

CLOCKS

CLK_T

CLK_I

MICRO_CLK

SAMPCLK

SIGN0 AND MAG0

SIGN1 AND MAG1

TRACKING

MODULE

CHANNEL 11

TRACKING

MODULE

CHANNEL 3

TRACKING

MODULE

CHANNEL 2

TRACKING

MODULE

CHANNEL 1

TRACKING

MODULE

CHANNEL 0

●

32-BIT BUS BUS

INTERFACE

STATUS

REGISTERS

ADDRESS

DECODER

SELECTS A<9:2>

D<15:0>

CONTROL

SYSTEM

STATUS

BITS

LATCHED

SIGN1 AND MAG1

LATCHED

SIGN0 AND MAG0

CLOCK

GENERATOR

SAMPLE

LATCH

INTERNAL

SAMPCLK

VDD

VSS

POWER

SUPPLY

TIC

MEAS_INT

ACCUM_INT

TIMEBASE

GENERATOR

Figure 4 Correlator block diagram

Timebase Generator

The Timebase Generator produces four important timing

signals: ACCUM_INT, TIC, MEAS_INT and TIMEMARK.

ACCUM_INT is an interrupt provided to control data

transfer between the correlator accumulators and the

microprocessor. It may be detected by means of the

ACCUM_INT output or by reading the

ACCUM_STATUS_A register (where bit 15 is a flag

indicating that ACCUM_INT has occurred since the

previous read of this register). ACCUM_INT is cleared by

reading ACCUM_STATUS_A.

After power-up this interrupt occurs every 505·05µs. Its

period can subsequently be changed in one of 3 ways:

1. By toggling the FRONT_END_MODE bit of the

SYSTEM_SETUP register,

2. By toggling the INTERRUPT_PERIOD bit of the

SYSTEM_SETUP register, or

3. By writing directly to the PROG_ACCUM_INT register.

See section Detailed Description of Registers on page 28

for more information.

GP2021

TIC is an internal signal with a default period of 99999·90µs.

It is used to latch measurement data (Epoch count, Code

phase, Code DCO phase, Carrier DCO phase and Carrier

cycle count) of all 12 channels at the same instant. Its

period can subsequently be changed, by writing to the

PROG_TIC_HIGH and PROG_TIC_LOW registers, or

toggling the FRONT_END_MODE bit of the

SYSTEM_SETUP register.

MEAS_INT is a signal derived from the TIC counter. It may

be used by the microprocessor as a software module

switching interrupt either by using the MEAS_INT output

or by reading the ACCUM_STATUS_B or

MEAS_STATUS_A register. MEAS_INT is activated at

each TIC and 50ms before each TIC so long as the TIC

period is greater than 50ms. If the TIC period is less than

50ms, MEAS_INT is activated only at each TIC. It is cleared

by reading either the ACCUM_STATUS_B or

MEAS_STATUS_A register, depending upon the

MEAS_INT_SOURCE bit of the SYSTEM_SETUP

TIMEMARK is also derived from TIC and may be output

on one of the discrete output pins. This signal is intended

to be used as an accurate 1 pulse per second timing

reference, aligned to UTC (Co-ordinated Universal Time),

with a pulse width of 1ms. A true 1pps output needs

extensive software algorithms to be produced; without this

the TIMEMARK will not be aligned to UTC.

TIMEMARK has two methods of operation but in both

cases TIMEMARK rising edges are generated coincident

with the rising edges of TIC. Therefore, for TIMEMARK to

be aligned with UTC, TIC must be aligned with UTC. This

is done by modifying the TIC period for a single TIC cycle,

then setting it back to its original value, thus slewing the

phase of TIC. TIMEMARK may be generated by setting

the TIMEMARK_ARM bit in the TIMEMARK_CONTROL

edge at TIMEMARK and clear the TIMEMARK_ARM bit.

Alternatively TIMEMARK may be generated as a

programmable integer number of TlCs, again under the

control of the TIMEMARK_CONTROL register.

Status Registers

There are four status registers (ACCUM_STATUS_A, _B,

_C and MEAS_STATUS_A). These contain flags

associated with the accumulated and measurement data

held on each of the 12 channels. Some system level status

bits also appear in these registers.

Sample Latches

The Sample Latches synchronise data from the front end

to the internal SAMPCLK. In Real_lnput mode the down

converted satellite signal can be sampled at the output of

the front end by SAMPCLK. This data is then input to the

GP2021 as 2-bit data on either the SIGN0, MAG0, or

SIGN1, MAG1 inputs, where it is re-sampled at the next

rising edge of SAMPCLK. These signals are then

distributed to the 12 tracking modules.

When a GP2015 or GP2010 front end is used, the data

represents a band-limited signal at an IF centered on

4·309MHz. Sampling at 5·714MHz aliases it to an IF of

1·405MHz.

In Complex_lnput mode, the down converted satellite signal

is applied direct to the GP2021 at its SIGN0, MAG0, SIGN1

and MAG1 inputs, which act as In-Phase Sign, In-Phase

Magnitude, Quadrature Sign and Quadrature Magnitude

respectively. These signals are sampled at 5·833MHz

within the correlator and then passed to the tracking

modules.

Address Decoder

The Address Decoder performs address decoding for the

correlator.

Bus Interface

The Bus Interface controls the transfer of data between

the external 16-bit wide data bus and the internal 32-bit

data bus.

Apart from the code and carrier DCO increment values,

all data transfers are 16 bits wide. Write operations to the

code and carrier DCOs are 32- bit data transfers, in which

the high 16-bit word must be written immediately before

the low 16-bit word. Note that the write cycle to write cycle

delay of 300ns referred to in the Microprocessor Interface

does not apply between the first and second write cycles

for 32-bit DCO data transfers. For further information see

the Microprocessor Interface section, page 15

Tracking Modules

The Tracking Modules are 12 identical signal tracking

channels numbered CH0 to CH11, each with the block

diagram shown in Figure 5. These blocks generate the

data used to track the satellite signals. There is no overwrite

protection mechanism on this data. For further information

see the section on Controlling the GP2021, page 24

Each Tracking Channel can be individually programmed

to operate in either Update or Preset mode. Update mode

is the normal mode of operation. Preset mode is a special

mode of operation where writes to certain registers are

delayed until the next TIC to allow synchronisation of

registers and presetting of the code DCO phase. For further

information see the Preset Mode section in the Detailed

Operation of the GP2021, page 28.

GP2021

16-BIT ACCUMULATE

AND DUMP - Q_PROMPT

16-BIT ACCUMULATE

AND DUMP - Q_TRACKING

CODE

SLEW

C/A CODE

GENERATOR

CODE

DCO

CODE

PHASE

COUNTER

EPOCH

COUNTERS

ACCUMS, CODE PHASE, ETC.

16-BIT ACCUMULATE

AND DUMP - I_TRACKING

16-BIT ACCUMULATE

AND DUMP - I_PROMPT

CARRIER

DCO

CARRIER

CYCLE

COUNTER DUMP

IN AND OUT

DATA BUSES

SOURCE

SELECTOR

SELECT

SOURCE

AND

SELECT

MODE

SIGN 0

AND

MAG 0

SIGN 0

AND

MAG 0

61, 62, 63, 66

61, 6361, 626161, 0

ILO ILO OR QLO

The indvidual sub-blocks in the tracking modules are:

Carrier DCO

The Carrier DCO, which is clocked at the SAMPCLK

frequency, is used to synthesise the digital local oscillator signal

required to bring the input signal to baseband in the mixer

block, and must be adjusted away from its nominal value to

allow for Doppler shift and reference frequency error.

When used with the GP2015/GP2010 the nominal

frequency of this signal is 1·405396825 MHz (with a

resolution of 42·57475mHz) and is set by loading the 26-

bit register CHx_CARRIER_DCO_INCR. This very fine

resolution is required so that the DCO will stay in phase

with the satellite signal for an adequate time. The Carrier

DCO Phase cannot be directly set, but must be adjusted

by altering the frequency.

The Carrier DCO outputs are 4-level, 8-phase sinusoids

with the sequences over one cycle as shown in Table 4.

As the clock to the DCO is normally less than 8 times the

output frequency, not all phases are generated in every

cycle. With a typical clock frequency of 5·714 MHz and an

output frequency of 1·405 MHz there are only about

4 phases per cycle. These will slide through the cycle as

time progresses to cover all values.

Code DCO

The Code DCO is similar to the Carrier DCO block. It is

also clocked at the SAMPCLK frequency and synthesises

the oscillator required to drive the code generator at twice

the required chipping rate. The nominal frequency of the

output is 2·046 MHz, to give a chip rate of 1·023 MHz and

is set by loading the 25-bit register

CHx_CODE_DCO_INCR.

It is programmed with a resolution of 85·14949 mHz when

used with a GP2015/GP2010 front end. Again, the very

fine resolution is needed to keep the DCO in phase with

the satellite signal. The Code DCO Phase can only be set

to the exact satellite phase in Preset mode. In Update

mode, it must be aligned with the satellite phase by

adjusting its frequency.

Destination Arm Sequence

Table 4 Carrier DCO outputs

Figure 5 Tracking module block diagram

ILO

QLO

21 11 12 12 11 21 22 22

12 12 11 21 22 22 21 11

GP2021

Carrier Cycle Counter

The Carrier Cycle Counter is 20 bits long, and keeps a

count of the number of cycles of the Carrier DCO between

TlCs. This is not needed for a basic navigation system but

may be used to measure the range change (delta-range)

to each satellite between TlCs. The delta ranges can be

used to smooth the code pseudo-ranges. For finer detail

the Carrier DCO phase may also be read at each TIC to

give the fractional part of the cycle count or delta-range.

C/A Code Generator

The C/A Code Generator generates the selected Gold code

for a GPS satellite (1 to 32), a ground transmitter

(pseudolite, 33 to 37), an INMARSAT-GIC satellite (201 to

211) or a GLONASS satellite. A Gold code is selected by

writing a specific pattern of 10 bits, as listed in the Detailed

Description of Registers section, to the CHx_SATCNTL

GLONASS code. Two outputs are generated to give both

a PROMPT and a TRACKING signal. The TRACKING

signal can be set to one of four modes: EARLY (one half

chip before the PROMPT signal), LATE (one half chip

behind), DITHERED (toggled between EARLY and LATE

every 20ms) or EARLY–MINUS–LATE (the signed

difference).

The output code is a sequence of 1s and 1s for all

code type sexcept EARLY–MINUS–LATE where the result

can also be a 0. To avoid having an unused LSB in the

accumulators, the values in EARLY–MINUS–LATE mode

are halved from the 2, 0, 2 that results from the

calculation (1 or 1 ) (1 or 1) to 1, 0, 1. This

must be considered when choosing thresholds in the

software, as the correlation results will be exactly half of

the values otherwise expected.

At the end of every code sequence (1023 chips in GPS

mode or 511 chips in GLONASS mode) a DUMP signal is

generated to latch the accumulated data for use by the

signal tracking software. Each channel is latched

separately, because the satellite signals are not received

in phase with each other.

The nature of GLONASS signals is that they are modulated

with the same PRN Gold Code, but are separated in the

frequency domain (1597MHz to 1617MHz). Navstar GPS

signals are modulated with different PRN Gold Codes, but

are transmitted on the same frequency (L1 = 1575.42MHz).

For the GP2021 to effectively demodulate GLONASS

signals, it would ideally need to have a separate set of RF

signal inputs for each correlator channel, in order for it to

differentiate between the different frequencies used by

each GLONASS satellite. Since this facility is not available,

the GP2021 cannot be used effectively to decode a

constellation of GLONASS signals.

Although the GP2021 contains a C/A code generator which

can be used to demodulate GLONASS signals (selected

by setting the GPS_NGLON bit in CHx_SATCNTL to 0),

the GP2021 does not have a sufficiently wide Doppler-

offset compensation range to allow it to be used effectively

for GLONASS. The total frequency offset, which the carrier

DCO can cope with, is 2·857MHz. This means that the

GP2021 will not be able to deal with the complete range of

GLONASS signals, unless they are mixed separately down

to a digital IF of approximately 1·4MHz.

The GP1020, also available from Zarlink Semiconductor , has

10 separate sets of SIGN/MAG inputs from RF front end

devices, which can be configured to connect independent

to any of 6 correlator channels, making this device more

suitable for GLONASS applications. Contact your regional

Zarlink sales office for more information.

Source Selector

In Real_lnput mode the Source Selector selects which input

signal pair to use (SIGN0/MAG0 or SIGN1/MAG1). In

Complex_lnput mode SIGN0/MAG0 are passed to the

In-phase arm and SIGN1/MAG1 to the Quadrature arm.

The data is treated as having the values shown in Table 5

(in both modes).

SIGN

3

1

1

3

Value

MAG

Table 5 SIGN/MAG values

Carrier Mixers

The Carrier Mixers multiply the digital input signal by the

Carrier DCO digital local oscillator to generate a signal at

baseband. In Real_lnput mode both I and Q Carrier DCO

phases are directed to the appropriate mixers. In

Complex_lnput mode a single In-Phase Carrier DCO

output is used in both mixers since the input signal is

already in I and Q form. The mixing of the Carrier DCO

outputs with the input signal produces a baseband signal

which can have the values 1,2, 3 and 6.

Code Mixers

The Code Mixers multiply the I and Q baseband signals

from the Carrier Mixers with both the PROMPT and

TRACKING local replica codes to produce four separate

correlation results. The correlation results are passed to

the Accumulate and Dump blocks for integration.

Accumulate and Dump

The Accumulate and Dump blocks integrate the Mixer

outputs over a complete code period of nominally 1ms.

There are 4 separate 16-bit accumulators for each channel.

GP2021

These represent the correlation of the I and Q signals with

the PROMPT and TRACKING codes, over the integration

period. There is no overwrite protection mechanism on

these registers so the data must be read before the next

DUMP.

Code Phase Counter

The Code Phase Counter counts the number of half-chips

of generated code and stores this value in the

CHx_CODE_PHASE register on each TIC.

Code Slew Counter

The Code Slew Counter is used to slew the generated

code by a number of half chips in the range 0 to 2047. In

Update mode the slew occurs following the next DUMP. In

preset mode it occurs at the next TIC. All slew operations

are relative to the current code phase. The Code Slew

counter must be written to each time a slew is required.

During the slewing process the accumulators for the

channel being slewed are inhibited so that the first result

is valid. If a slew is written while a channel is disabled it will

occur as soon as the channel is enabled.

Epoch Counter

The Epoch Counters keep track of the number of code

periods over a 1 second interval. This is represented by a

5-bit word for the number of 1ms integration periods (0 to

19), plus a 6-bit word containing the number of 20ms counts

(0 to 49). The Epoch Counters can be pre-loaded to

synchronise them to the data stream coming from the

satellite. This value will be transferred immediately to the

counter when in Update mode, or after the next TIC if in

PRESET Mode.

The Epoch Counter values are latched on each TIC into

the CHx_EPOCH register. In addition the instantaneous

values are available from the CHx_EPOCH_CHECK

PERIPHERAL FUNCTIONS

The following section describes the Dual UART, Real Time

Clock and Watchdog, Power and Reset Control and

Discrete l/O blocks.

Dual UART

A Dual UART is included for serial communications. It has

two identical blocks, UART_A and UART_B, each

containing separate transmit and receive channels. The

parity and separate transmit and receive baud rate can be

configured independently for each UART. Each uses a

polled processor interface and each transmit and receive

channel has an 8- byte deep FIFO.

For further information on UART registers refer to the Detailed

Description of Registers and Figure 11 (page 28).

A typical serial data stream is shown in Fig. 6. The Parity

bit is optional and if no parity is selected the time slot for it

is removed from the data stream and the Stop bit follows

immediately after the last data bit in both transmit and

receive directions. Note that the LSB is always preceded

by a Start bit. Table 6 shows possible UART configurations.

START

FIRST

STOP

LAST

D8 D9 D10 D11 D12 D13 D14 D15 P

LSB MSB PARITY

(OPTIONAL)

Figure 6 Serial data waveform

Start bits

Data bits

Stop bits

Parity

Flow control

Transmit FIFO depth

Receive FIFO depth

FIFO speed

Data rate

Value

1 bit low

8 bits Logic 0 = low, Logic 1 = high

1 bit High

Odd/even/none

None

8 bytes

Transmit FIFO write rate and Receive FIFO read rate maximum is one byte per 230ns.

The maximum buffer through delay is 2s.

300, 600,1·2k, 2·4k, 4·8k, 9·6k, 19·2k, 38·4k and 76·8k baud. Transmit and Receive

rates individually configured.

Parameter

Table 6 UART functionality

GP2021

Reset

It is possible for the software to reset either UART

independently via the RESET_CHx registers. A hardware

reset affects both UARTs. During a UART reset, the

contents of all Control and Status registers will be cleared.

In addition the Transmit and Receive FlFO’s will be emptied

and the TX outputs will be held low.

Channel Loopback

For system test purposes, a loopback facility is provided

for each channel, controlled by the Configuration registers.

In loopback, the TX output is set high.

Real Time Clock (RTC) and Watchdog

This block consists of a 32·768kHz crystal oscillator, a fixed

divider, a 24-bit counter, a Watchdog function and three

8-bit data registers. XIN and XOUT are the crystal in and

crystal out connections to the oscillator circuit. A recom-

mended crystal oscillator circuit is shown in Fig. 7. When

the Real Time Clock is not being used, XIN must be tied

low.

The first divider is a fixed divide-by-32768 giving a 1Hz

output. The counter then counts seconds, giving a

maximum time of 194 days. The time is output in three

8-bit registers with the data being latched when a read is

performed to the LS register (the register holding the least

significant byte of the clock data). On reaching its maximum

count, the count is frozen (i.e. all ones), until being reset.

In Power Down mode the Real Time Clock continues to

run, but the data registers cannot be accessed. When

normal power is restored, the software can determine the

elapsed time whilst in Power Down mode, thereby assisting

in estimating the current position of GPS satellites and so

reducing Time-To-First-Fix.

TheWatchdog generates a System Reset (see Powerand

Reset Control) if the Watchdog Reset address has not

been written to for a period of approximately 2 seconds.

The watchdog function is inhibited whilst in Power Down

mode and can be disabled via a bit in the System

Configuration register.The software is able to reset the Real

Time Clock and Watchdog via the Clock Reset and

VOLTAGE

SENSOR POWER_GOOD

VSS VSS

VDD

BATTERY SUPPLY

15V SUPPLY

GP2021

Watchdog Reset registers respectively. In addition, the

watchdog is reset during a System Reset.

For further information on the registers refer to the Detailed

Description of Registers (page 28).

Power and Reset Control

This block performs two functions: Power Control and

System Reset Generation

Power Down Mode

In order to allow power conservation within a battery backup

system, the GP2021 provides a Power Down mode, in

which the supply voltage may drop to a minimum of 2·2V,

thereby minimising the supply current. In this mode all

functions within the GP2021 are disabled except for the

Real Time Clock.

The GP2021 is placed in Power Down mode by taking the

POWER_GOOD pin Low. In ARM System mode with the

NBRAM pin held low, the initiation of Power Down mode

is delayed until just after a falling edge of MICRO_CLK so

as not to corrupt battery backed RAM. Fig. 8 shows a

suggested circuit implementation. Table 7 shows output

logic levels in Power Down mode.

In Power Down mode all inputs and l/Os except

POWER_GOOD and XIN are internally switched to known

logic levels to prevent extraneous switching from causing

excessive power consumption, and may therefore be left

floating. All the l/O pins (D<15:0>, MULTI_FN_IO and

DISCIO) have their output drivers driven to the high

impedance state.

VSS

32·768kHz

CRYSTAL

10M

VSS

680k

22p 22p

XIN XOUT

Figure 7 Recommended crystal oscillator circuit

Figure 8 Suggested battery back up configuration

GP2021

NW<3:0>/NC

NRD/NC

NRAM

(standard interface mode)

NRAM

(ARM system mode)

NROM/NC

NSPARE_CS/NC

NEEPROM/NC

TXATXB

ACCUM_INT

MEAS_INT

ABORT_MICRO_CLK

MCLK / NC

ARM_ALE / NC

DBE / NC

NRESET_OP

DISCOP

SAMPCLK

XOUT

Logic Level

Low

NB RAM

High impedance

Low

High impedance

Low

High Impedance

Low

Active

Pin Name

Table 7 Output logic levels in Power Down mode

1. POWER_GOOD. A hardware reset will occur if this pin

is taken iow, as shown in Figure 9. The purpose of this

input is to detect a power failure. If the NBRAM pin is held

iow in ARM System mode, the internal Power Down mode

is not entered until about 6ns after the falling edge of

MICRO_CLK, otherwise it is entered immediately. This allows

for RAM write cycles to complete sensibly when battery

backed-up RAM is used, with no corruption of RAM data.

2. Watchdog. An expiry of the watchdog will result in a

hardware reset as shown in Fig. 10. This reset will clear

the watchdog whose time-out period is 2-3 seconds.

3. PLL_LOCK. The PLL_LOCK pin is used to indicate

(when high),that the phase locked loop in the RF front end,

which generates the master clock, is in lock. This signal is

filtered within the GP2021 and the reset state associated

with it is only de-activated if the PLL_LOCK input has been

high for approximately 50 ms as shown in Figure 11.

In addition to the three reset sources described above, an

active low NRESET_IP pin is available in Standard

Interface mode if the system resets are to be generated

externally. Figure 12 shows a NRESET_IP generated reset.

Note that the NRESET_OP pin will go high four

MICRO_CLK cycles after all hardware reset sources have

cleared. This fulfills the reset requirements of the ARM60

microprocessor. For information on the state of the registers

following a hardware reset refer to the Detailed Description

of Registers on page 28.

System Error Status Register

This allows the software to determine whether the source

of a hardware reset was from a power failure, a PLL_LOCK

failure, watchdog timeout or from an external reset in

Standard Interface mode. For further information refer to

the Detailed Description of Registers.

Hardware Reset Generation

The manner in which a hardware reset occurs depends

on whether the GP2021 is in ARM System mode or

Standard Interface mode. During a hardware reset, the

NRESET_OP pin is taken Low and the reset signal is

applied within the GP2021 to all blocks except the Real

Time Clock.

There are three sources of hardware resets common to

both ARM System and Standard Interface modes, with an

additional source in Standard Interface mode:

POWER DOWN

MODE

4 CYCLES

POWER_GOOD

NRESET_OP

MICRO_CLK/MCLK

Figure 9 POWER_GOOD hardware reset generation (NARMSYS = 0, NBRAM = 0)

Figure 10 Watchdog hardware reset generation

122µs

4 CYCLES

WATCHDOG

NRESET_OP

MICRO_CLK/MCLK

GP2021

4 CYCLES

PLL_LOCK

NRESET_OP

MICRO_CLK

50ms

MCLK

Figure 11 PLL_LOCK hardware reset generation

4 CYCLES

NRESET_IP

NRESET_OP

MICRO_CLK

Figure 12 NRESET_IP hardware reset generation

Discrete l/O

The GP2021 contains a numberof pins which may be used

as discrete inputs or discrete outputs for general purpose

system monitoring and control applications. The actual pins

which may be used for each function vary according to the

application and the interface mode of the GP2021. Table 8

shows a list of possible discrete inputs and outputs and

the modes in which they may be used. The level on all

discrete inputs can be read from the IO_CONFIG register.

The status of the DISCIP pin may also be read from

ACCUM_STATUS_B. The discrete outputs are controlled

via either the SYSTEM_SETUP or IO_CONFIG registers.

NRW/DISCIP3

NOPC/NINTELMOT

NMREQ/DISCIP2

NBW/WRPROG

DISCIO

NBRAM/DISCIP4

MULTI_FN_IO

SIGN0, MAG0

SIGN1, MAG1

DISCIP1

RXA

RXB

DISCOP

DISCIO

MULTI_FN_IO

Pin name

Discrete inputs

Read location Conditions for use as a discrete input

Standard Interface mode.

ARM System mode (debug disabled).

Standard Interface mode.

Motorola mode only.

DISCIO configured as discrete Input.

Standard Interface Mode.

MULTI_FN_IO configured as discrete input.

Single real input mode (GP2010 or GP2015) front end using SIGN0, MAG0.

Single real input mode (GP2010 or GP2015) front end using SIGN1, MAG1.

Always available - dedicated Discrete Input.

UART Channel A not used.

UART Channel B not used.

High, low, CH0 dump, TIMEMARK, 100kHz Square Wave, scan out.

High, low, TIMEMARK, 100kHz Square Wave.

IO_CONFIG

ACCU M_STATU S_B

IO_CONFIG

SYSTEM_SET_U P

IO_CON FIG

IO_CONFIG

Discrete outputs

Pin name Config. location Possible outputs

Table 8 Discrete input/output configuration

GP2021

3. The PLL_LOCK input and its associated 50ms delay as

a reset source is overridden. This removes the dependency

on the presence of the front end circuit.

MICROPROCESSOR INTERFACE

The Microprocessor Interface of the GP2021 is compatible

with most 16- and 32-bit microprocessors. It can be

configured for either ARM System mode or Standard

Interface mode by means of the NARMSYS pin.

In Standard Interface mode, two mode control pins,

NINTELMOT and WRPROG, are provided. NINTELMOT

selects between Intel and Motorola style interfaces, with

WRPROG selecting either Intel i486 or 80186 style

interfaces. See Table 9 for more details.

Digital System Test Interface

The GP2021 contains a Digital System Test mode to allow

testing of the digital section of the system board. Provided

that the MULTI_FN_IO pin is high, this mode is enabled

subsequent to a hardware reset or a write of specific data

to the IO_CONFIG register. The enabling of Digital System

Test mode has three effects:

1. The master clock inputs, CLK_T and CLK_I, are replaced

by the signal on the RXA pin. This allows the GP2021 to

be clocked synchronously with the board tester which is

relevant in ARM System mode where the GP2021

produces the main processor clock to the ARM60.

2. The RXB pin becomes the active high RTC Reset input.

This is mainly intended for factory testing of the GP2021,

allowing the RTC to be reset on power up, but may also be

used to disable the RTC and Watchdog circuits in this mode.

NARMSYS

Mode

ARM system

Standard interface

WRPROG

Processor

ARM60

Motorola style

Intel 80186 style

Intel 486 style

General Interface Timing

In addition to the detailed timings associated with individual

read and write cycles (see Electrical Characteristics), the

internal architecture of the correlator also imposes limits

on cycle to cycle timings (in particular write to write cycle

and write to read cycle). For a simple microprocessor

interface, it must be ensured that no attempts are made to

access the correlator for the 300ns following the end of a

correlator write cycle in Real_lnput mode, or 314ns in

Complex_lnput mode. However, if the controlling software

is to be allowed to write rapidly to the correlator (e.g. block

writes), then a more complex bus interface (which inserts

wait states) will be required. Note that this limitation only

applies after correlator writes, not peripheral function writes

and also does not apply to writes to the correlator

X_DCO_INCR_HIGH address.

The correlator section of the GP2021 uses a multi-phase

clock internally, and the correlator registers load on specific

clock phases. At the end of a write cycle, the falling edge

of the internal write strobe latches both the relevant address

and data bits. This data is then loaded from the internal

data bus to the relevant register at some time during the

following 300ns for Real_lnput mode or 314ns for

Complex_lnput mode. A write cycle to the Correlator with

no writes in the preceding 300ns (314ns) may be performed

immediately, so long as the detailed signal timings are met.

However, subsequent read or write cycles to the Correlator

after this write cycle may need to be delayed if they would

otherwisw modify the internal address or data lines.

Correlator read cycles with no write cycles in the preceding

300ns (314ns) are self-contained, and do not delay

subsequent cycles. An isolated read cycle requires only

sufficient wait states to meet the detailed signal timings.

Write Cycle To Read Cycle Timings

As described previously, the internal write cycle of the

Correlator takes 300ns (314ns). Only once the write cycle

is complete will the correlator address decoders switch to

decoding the current address. The correlator uses a pre-

charged internal data out bus and hence the decoded

address lines must be stable before the internal bus drivers

are enabled (when the read strobe goes high).

Consequently, the read strobe must be held low until some

time after the end of the 300ns (314ns) internal write cycle,

to allow sufficient internal address setup time. For the exact

timing requirements see the Timing Characteristics.

Write Cycle To Write Cycle Timings

The internal write cycle of the correlator takes 300ns

(314ns) after the falling edge of the write strobe. During

this time the write internal address and data buses (latched

by write) must not be modified. If a second write follows

the first, the second write cycle must be delayed such that

it ends no earlier than 300ns (314ns) after the end of the

previous write, the ‘end’ being a falling edge on the internal

write strobe. The specific interface signal timings must also

be met.

Notes about Interface Timing Constraints

It should also be noted that these timings need only be

met for correlator accesses, not support function accesses,

since these use self-contained write cycles and are not

Table 9 Microprocessor interface configuration

NINTELMOT

GP2021

clocked by the multi-phase clocks. In addition, writes to

the Correlator register X_DCO_INCR_HIGH need not incur

subsequent delays since writes to this location do not

instigate an internal write cycle. A write to this address

must always be followed by a write to either a

CHX_CARRIER_DCO_INCR_LOW register or a

CHX_CODE_DCO_INCR_LOW register and it is this

second associated write which instigates the internal write

cycle.

In ARM System mode all these timing requirements are

handled by the internal memory manager.

Note that the exact number of wait states which need to

be inserted after a correlator write is not fixed. If the

processor were to perform a correlator write then spend

400ns accessing a different peripheral, subsequent

correlator reads and writes would incur no additional delay.

It is anticipated that correlator wait states will be generated

by either one or two external counters, preset on the falling

edge of a correlator write, and which then count down to

zero. Only once the counter has reached zero may the next

correlator access either complete (write) or start (read) A series

of correlator reads and writes are shown in Figure 13.

WRITEREADREAD DELAYED WRITE DELAYED READ READ

WREN

READ

NCS

A<9:2>

D<15:0> 0P 0P IP IP 0P 0P

300ns (314ns) 300ns (314ns)

NOTE: OP and IP are with respect to the GP2021. OP denotes a GP2021 output, IP denotes a processor output

Figure 13 Correlator bus timing – write to write and write to read

MEMORY

NRAM

NROM

NEEPROM

NSPARE_CS

NW<3:0>

NRD

D<15:0>

A<9:2>

A<19:10>

DBE

ARM_ALE

MCLK

NRW

NMREQ

NBW

D<15:0>

A<9:2>

A<19:10>

A<22:20>, A<1:0>

NOPC

ABORT

ARM60

GP2021

NRESET_OP, ACCUM_INT and MEAS_INT not shown

Figure 14 ARM system mode

GP2021

ARM System Mode

ARM System Mode, as shown in Figure 14, allows

the GP2021 to be interfaced with an ARM60

microprocessor and external memory devices (i.e RAM,

ROM, EEPROM, EPROM, Flash) without the need for

external glue logic.

Address Map

Both the GP2021 and external memory devices are

memory mapped into 1Mbyte segments by A<22:20> as

shown in Table 10.

Decoded

output pin

NROM

NRAM

NEEPROM

NSPARE_CS

Device

selected

ROM

RAM

Correlator

Support functions

EEPROM

User defined

Not decoded

A22 A21 A20

Table 10 ARM system address map

and the control signals ARM_ALE and DBE to match the

timing requirements of the various memory devices .

The memory interface is via the memory chip select lines

(NRAM, NEEPROM, NROM and NSPARE_CS), the Read

line (NRD) and the byte write select outputs (NW<3:0>).

ARM System Timing

The GP2021 timing diagrams for each of the memory

interfaces (EEPROM, RAM, ROM, SPARE), and ARM60

are shown in the Electrical Characteristics.

Wait State Generation

To allow access to slow peripherals or memory, the clock

(MCLK) to the ARM60 microprocessor may be stretched

in either Phase 1 (low) or Phase 2 (high), thus allowing

wait states to be introduced (where a wait state is defined

as being one MCLK period).

The GP2021 introduces one wait state for accesses to the

Real Time Clock, Dual UART and System Control registers,

as shown in Figure 15. Correlator accesses as shown in

Figure 19 incur one wait state; subsequent accesses being

prevented from contravening the Correlator requirements

(see Correlator Functional Description) by adding several

wait states.

In order to ensure compatibility with a variety of memory

devices, the ROM interface is programmable with between

one to three wait states, while the EEPROM and SPARE

interfaces can be programmed with between three to six

wait states via the Wait State Register.

For further information on the Wait State Register, refer to

Detailed Description of Registers. Read and write cycles

for the RAM, EEPROM (or Spare) and ROM interfaces

are shown in Figures 16 through18.

During a read cycle from Flash memory, the output disable

to data bus release time, could be greater than 25ns. Hence

in order to avoid bus contention, the nominal period of

MCLK is stretched by 25ns during the following cycle.

The ARM60 is able to perform either byte or word (4 bytes

wide) writes to memory. All registers within the GP2021

are word aligned, with only write accesses to external RAM

being either byte or word aligned. The signal NBW is used

to indicate either a byte or word write request, with A<1:0>

performing byte selection.

Decoding of NBW and A<1:0> is performed by the

Microprocessor Interface, with NW<3:0> being the byte

write select outputs to memory. During a word write all

four of the outputs NW<3:0> will be active.

Note that the register addresses for the Correlator and

Support Functions are as shown in the GP2021 Register

Map.

Control Signals

The GP2021 uses the ARM60 control signals NBW,

NMREQ and NRW to generate the processor clock MCLK

GP2021

20MHz

INTERNAL

CLOCK

MCLK

NRW

A<22:20>, A<9:0>

D<15:0>

ARM_ALE

NMREQ

VALID VALID

NBW

DBE

INTERNAL WRITE

INTERNAL READ

Figure 15 Peripheral functions write/read cycle

A<22:20>, A<9:0>

20MHz

INTERNAL

CLOCK

MCLK

NRAM

D<15:0>

NOTE: This diagram assumes NMREQ is low

ARM_ALE

NW0

NRD

VALID VALID VALID VALID VALID VALID

NW1

NW2

NW3

DBE

NRW

NBW

Figure 16 RAM read/write cycle

GP2021

20MHz

INTERNAL

CLOCK

MCLK

NROM

A<22:20>, A<9:0>

D<15:0>

NOTE: NRW, NMREQ and DBE are assumed to be low

ARM_ALE

NEEPROM

NRD

Figure 17 ROM (1 wait state) and EEPROM/spare (211

11 wait states) read cycles

20MHz

INTERNAL

CLOCK

MCLK

NEEPROM

A<22:20>, A<9:0>

D<15:0>

NOTE: NBW and NRW are assumed to be high for this cycle

ARM_ALE

NW<3:0>

DBE

Figure 18 EEPROM (or Spare) write cycle

20MHz

INTERNAL

CLOCK

MCLK

NRW

A<22:20>, A<9:0>

D<15:0>

NOTE: NBW is high and NMREQ low

ARM_ALE

INTERNAL

WRITE

DBE

INTERNAL

READ

VALID VALID VALID

Figure 19 Correlator write and read cycles

GP2021

Debug (Abort) Function

This is a feature designed to aid debugging and functions

as follows: ln ARM System Mode, the MULTI_FN_IO pin

can be configured as a TRIGGER input to the Debug block

via the IO_CONFIG register (see Detailed Description of

Registers). In this mode a rising edge at the MULTI_FN_IO

pin will generate a valid ARM data Abort sequence at the

ABORT pin as shown in Figure 20.

Standard Interface Mode

This mode allows the GP2021 to be interfaced to most

standard 16- and 32-bit microprocessors as shown in

Figure 21. No memory control is provided, so external glue

logic may be required in order to interface the

microprocessor to memory.

MCLK

NMREQ

NOPC

MULTI_FN_IO

ABORT

Figure 20 Debug (Abort) function timing

ADDRESS

DECODE

LOGIC

MICRO_CLK

NCS

ALE_IP

WREN

READ

D<15:0>

A<9:2>

VDD OR VSS NINTELMOT

VDD OR VSS WRPROG

VDD NARMSYS

GP2021 MICROPROCESSOR

Figure 21 Standard interface mode

Control Signals

In Standard Interface Mode (NARMSYS held high), the

microprocessor interface of the GP2021 consists of two

mode control pins, NINTELMOT and WRPROG, and the

control signals themselves, ALE_IP, NCS, WREN and

READ, the exact function of which is dependent upon the

interface style selected.

Motorola Style Interface (NINTELMOT = 1,

WRPROG = X)

The WRPROG mode control pin is not used in Motorola

Interface mode and should be tied high or low. The ALE_IP

(Address Latch Enable input) pin is used to transparently

latch the address lines A<9:2> to the GP2021. If these

address lines are already latched externally, this pin may

be tied high. Note that the internal ALE signal is inhibited

during a read or write strobe so the address lines may be

changed once the read or write strobe has become active.

The WREN pin acts as a WRITE/READ ENABLE strobe

(active high) with the READ pin selecting either a READ

strobe (READ = 1) or a WRITE strobe (READ = 0). In a

similar way to the addresses being latched during a read

or write strobe, the READ signal is also latched during a data

strobe and may be changed towards the end of the cycle.

The NCS pin is an active low chip select used to gate out

the internal read and write strobes. In Standard Interface

Mode, the GP2021 can best be visualised in terms of three

signals, ALE_INT, WRSTROBE_INT and

RDSTROBE_INT, the internal ALE, write strobe and read

strobe signals. In Motorola Style Interface Mode these

signals are derived as follows:

ALE_INT= ALE_IP • (WRSTROBE_INT + RDSTROBE _INT)

WRSTROBE_INT = NCS • WREN • READ

RDSTROBE_INT = NCS • WREN • READ

INTEL 80186 Style Interface (NINTELMOT = 0,

WRPROG =’0')

In the 80186 Style Interface mode the ALE_IP acts as an

Address Latch Enable input (as in Motorola mode), used

to transparently latch the address lines A<9:2> to the

GP2021. As with Motorola mode, if the addresses are

latched externally this pin may be tied high. Whereas

Motorola mode used a single strobe input and a Read/

Write level to denote read and write strobes, both INTEL

modes use a pair of strobe inputs, one for reads, and one

for writes. In this mode, READ acts as the active low read

strobe ( READ = RDSTROBE) and WREN the active low

GP2021

write strobe (WREN = WRSTROBE). NCS is the active

low chip select used to gate out internal data strobes.

ALE_INT= ALE_IP

WRSTROBE_INT = NCS • WREN

RDSTROBE_INT = NCS • READ

INTEL 486 Style Interface (NINTELMOT = 0,

WRPROG = 1)

The Intel 486 style interface is similar to the 80186 style

interface, with similar separate read and write strobes.

Some of the later Intel microprocessors (notably the i486)

have a very short delay between the rising edge of ALE

and the falling edge of the read or write strobes. Due to

the pre-charged nature of the data out bus of the Correlator,

the address inputs must remain stable throughout the read

strobe, and the short delay from ALE to read strobe would

produce insufficient address setup times for correct

operation. The 486 style interface mode removes this

problem by gating both the read and write strobes such

that they are inhibited until the falling edge of ALE_IP. The

ALE_IP pin must not be tied high in 486 style interface

mode.

ALE_INT= ALE_IP

WRSTROBE_INT = NCS •WREN • ALE_IP

RDSTROBE_INT = NCS • READ • ALE_IP

Reset

The NRESET_IP pin allows the GP2021 to be provided

with an external system reset. For further information refer

to System Reset in Standard Interface Mode.

As shown in the GP2021 Register Map, Table 11, register

addresses differ from those in ARM system mode. In

particular in standard interface Mode the GP2021 address

bus interface is via A<9:2>, with NCS acting as its chip

select input. The address pins A0, A1 in ARM System Mode

now become the NRESET_IP and ALE_IP inputs. Hence,

depending upon the system configuration employed,

A<9:2>, of the GP2021 could be connected to the

microprocessor address pins A<7:0>.

SOFTWARE REQUIREMENTS

The very wide variety of types of GPS receiver need to

operate the correlator in different ways. So to accommodate

this and also to allow dynamic adjustment of loop

parameters, the GP2021 has been designed to use

software for as many functions as possible. This flexibility

means that the device cannot be used without a

microprocessor closely linked to it, but as a processor is

always needed to convert the output of the GP2021 into

useful information this is not a significant limitation.

The software associated with the GP2021 can be divided

into two separate modules:

1.Acquire and track satellite signals to give pseudo-ranges

2. Process pseudo-ranges to give the navigation solution

and format it in a form suitable for the user.

For the Navigation Solution to be possible all of the pseudo-

ranges must have exactly the same clock error, which can

then be removed iteratively to give real ranges if sufficient

satellites are tracked (three if the height is known, otherwise

four). This need for exact matching of timing errors explains

the need for all of the complicated synchronisation between

all 12 channels of the correlator.

The following relates only to the signal processing aspects

of the software, to acquire and track signals from up to

twelve satellites and to obtain the pseudo-ranges and the

navigation message. The operation of the navigation

software is not dependent on the details of the correlator,

and so does not need to be included in this data sheet.

A pair of on-chip interrupt timebase signals are provided

to help implement a data transfer protocol between the

microprocessor and the 12-channel correlator at fixed time

intervals; these signals are:

1. ACCUM_INT - used to interrupt the microprocessor to

retrieve accumulated data (1·023ms worth) -period of

interrupt normally less than 1ms.

2. MEAS_INT - used to interrupt the microprocessor to

retrieve Measurement data that occurs every TIC

(approximately 100ms period).

These interrupts can be used to achieve instant response

from the microprocessor via an Interrupt Service Routine.

Otherwise a software based polling scheme will be needed;

the choice is set by the application. If the ACCUM_INT

interrupt is used, and perhaps also if polling is used, the

data transfer rate is about twice the correlation result rate

for each channel, so many transfers will not give new data.

Bus use can be reduced by examining the status registers

before each transfer to see if new data is available and

then only reading the data if it is useful.

It is important to note that the timing of each ot the correlator

channels wlil be locked to its own incoming signal and not

to each other or to the microprocessor interrupts, so new

data is generated asynchronously. The sampling instant

of measurement data of all channels however is common

to give a consistent navigation solution.

In order to acquire lock to the satellites as quickly as

possible, the data from the last fix should be stored as a

starting point for the next fix. It is also useful to make use

GP2021

of the embedded real-time clock on the chip to give a good

estimate of GPS time for the next fix; the navigation

solutioncan be used to measure clock drift and calculate a

correction for the clock to overcome ageing. The user’s

location (or a good estimate of it) along with the Almanac

and the correct time will indicate which satellites should

be searched for. These may be used to find an estimate of

Doppler effects, while the previous clock error is the best

available estimate of the present clock error. If this

information is not available then the receiver must scan a

much wider range of values, which will greatly increase

the time to lock. The satellite Clock Correction and

Ephemeris are needed for the navigation solution, so if a

recent set is held in memory the calculations may begin

as soon as lock is achieved and not need to wait for the

Satellite Navigation message re-transmission (18 to 36

seconds).

The 12-channel correlator on the GP2021 contains four

different types of registers:

●Control Registers that are used to program functions

of the device.

●Status Registers that provide a status indication of the

process taking place in the device.

●Accumulated Data Registers that provide the results

of correlation with the C/A code every millisecond. This

is the raw data used to acquire and track satellite signals.

●Measurement Data Registers which latch the carrier

DCO phase, carrier cycle count, code DCO phase,

1millisecond epoch, and the 20 millisecond epoch count

at every 9·09 or 100 milliseconds interval. This is the

raw data used to compute pseudorange.

Software Sequence For Acquisition

The spectrum of each Navstar GPS satellite signal is

spread-spectrum modulated using 1023 chip Gold codes.

This causes the satellite signals seen by a GPS receiver

to be so weak that they are buried in the noise and can

only be detected by correlation. The GPS signal power at

a GPS receiver antenna is typically approximately

2130dBm, whereas the noise in the GPS signal band

(2·046MHz wide) is approximately 2111dBm at room

temperature. To correlate the received signals therefore,

a locally generated code must be chosen to precisely match

the spreading code type, rate, and phase.

This pattern is then multiplied bit-by-bit with the incoming

data stream and the results integrated over the code length

to recover the signal.

The process of signal acquisition is simply the matching of

receiver settings to the actual signal values. To make

matters more complicated the satellite carrier frequency is

shifted a little by the Doppler effect due to the motion of

the satellite, the user clock will drift randomly, and (in most

situations) the signal-to-noise ratio (SNR) is poor for some

satellites. As a result, the software must be ‘wideband’ to

find the signal and also ‘narrow band’ to reduce noise,

leading to very different programs in different applications.

For all tracking channels, the signal processing software

needs the following sequence of activities:

1. Program CHx_SATCNTL register to select the desired

GPS Gold code (PRN number) for the selected satellite

and also select the code type for the mode of the

correlator tracking arm. It is often best, when in

acquisition mode, to fix the tracking arm to Dithering

Mode (alternate ‘Early’ and ‘Late’) and do a search in

two phases at once and then switch to a tracking mode

once a satellite is found.

2. Program CHx_CARR_INCR_LO and

CHx_CARR_INCR_HI registers. The values

programmed into these two registers are concatenated

and are used to set the local oscillator frequency for the

digital mixing performed in the 12-channel correlator to

bring the incoming 2-bit digitised signal from the RF

front end down to baseband. The value to be

programmed is equal to the nominal local oscillator

frequency plus the estimated Doppler shift

compensation plus the estimated user clock frequency

drift compensation.

3. Program CHx_CODE_INCR_LO and

CHx_CODE_INCR_HI The value to be programmed

in these registers represents twice the nominal chipping

rate of the C/A code (2·046 MHz) plus, if desired, a

small compensation for the Doppler shift and user clock

frequency drift.

4. Release the tracking channel reset by programming

the RESET_CONTROL register with the proper value.

This will cause the correlation process to start.

5. Obtain accumulated data from Accumulated Data

same tracking channel can be added to increase, at

will, the integration period of the correlation.

6. Decide if the GPS signal has been found by

comparing the correlation result with a threshold. If found

then jump to a signal pull-in algorithm. Note that both

in-phase and quadrature phase accumulated data have

to be considered since at this time, the carrier DCO

local oscillator phase is not necessarily in phase with

the incoming GPS signal.

7. If the GPS signal has not been found, a new trial has

to be made with different carrier DCO, code DCO, or

Gold code phase programming. Typically, both DCOs

would be held constant while the Gold code phase is

varied to try all of the 2046 half chip positions possible,

then the carrier DCO would be programmed with slightly

different values and the Gold code phase positions

would again be scanned. The Gold code phase is varied

by programming the CHx_CODE_SLEW register and

can be varied by increments of half a code chip.

GP2021

8. Once the GPS signal has been found, the code phase

alignment, the carrier phase alignment and the Doppler

and user clock bias compensations are still coarse. The

code phase alignment is only within a half code chip,

the carrier DCO is not in phase with the incoming signal

and in frequency is still in error by up to the increment

used for successive trials.

The signal processing software must next use a pull-in

algorithm to refine these alignments. There are many

suitable types of algorithm to choose from, such as

successive small steps until the error is too small to matter,

like an analog PLL, or by using more complicated signal

processing to estimate the errors and jump to a much better

set of values. The signal pull-in algorithm will then program

CHx_CARR_INCR_LO/Hl registers with more accurate

values for the Carrier DCO. Corrections to the Gold code

phase smaller than a half chip cannot be done by

programming CHx_CODE_SLEW registers in the Code

Generator, but should set CHX_CODE_INCR_LO/_HI

registers to steer the Code DCO and gradually bring the

Gold code phase to the right value.

Signal Tracking

The incoming GPS signal will exhibit a Doppler shift that

varies with time due to the non-uniform motion of the

satellite relative to the receiver, and the user clock bias is

likely to also vary with time. The net result is that unless

dynamic corrections are applied to the code and carrier

DCOs, the GPS signal will be lost. This leads to two servo

loops being required: one to maintain lock on the Gold

code phase and a second to maintain lock on the carrier.

This can be implemented with the following.

The raw data used to steer the two servo loops is the

Accumulated Data, which is output by the tracking channel

at the rate of once per millisecond. The tracking arm

Accumulated Data is used for the Gold code loop; some

approaches use an ‘early minus late’ Gold code to

implement a null steering loop, others use a dithering code

which alternates between a code one half-chip late and a

code one half-chip early. In the GP2021, the dithering rate

is 20ms (20 code epochs) each way, starting with Early

after a reset, when this type of code is selected through

the CHx_CNTL register. The Gold code loop is closed by

regularly updating the code DCO frequency using the

CHx_CODE_INCR_LO/_HI registers.

The prompt arm Accumulated Data is used for the carrier

phase loop (although the dithering mode in the tracking

arm may also be used). One approach consists of varying

the carrier DCO phase in order to maintain all the correlation

energy in the in-phase correlator arm and none in the

quadrature phase correlator arm. The carrier phase loop

is closed by regularly updating the carrier DCO frequency

using the CHx_CARR_INCR_LO/_HI registers.

Data Demodulation

The C/A code is modulated with Space Vehicle (SV) data

at 50 Baud to give the navigation message. This modulation

is an exclusive-OR function of the C/A code with the SV

data. This means that every 20 milliseconds (which is every

20 C/A code epochs), the C/A code phase will be reversed

(shifted by 180 degrees) if the new data bit is different

from the previous one. On the prompt arm, once the signal

is being correctly tracked, such a data bit transition will

change the sign of the accumulated data. Data

demodulation can then be achieved in two stages:

1. Locate the instants of data bit transitions to identify which

C/A code epoch corresponds to the beginning of a new

data bit. This will allow initialisation of the GP2021 epoch

counters by the signal processing software (through the

CHx_1MS_EPOCH and CHx_20MS_EPOCH

registers) to count code epochs from 0 to 19 in phase

with data bits. At each new cycle of the 1ms epoch

counter, the 20ms epoch counter will increment.

2. Record the sign of accumulated data on the prompt

arm for each data bit period of 20ms, with filtering to

reduce the effect of noise on the signal. Note that there

is a sign ambiguity in the demodulation process in that

it is not possible to tell which data bits are zeros and

which are ones from the signal itself. This ambiguity

will be resolved at a later stage when the full Navigation

Message is interpreted.

Pseudorange Measurement

The measurement data registers provide the raw data

necessary to compute the pseudorange. This raw data is

a sample, at a given instant set by the TIC signal, of the

20ms and 1ms epoch counters, the C/A code phase

counter and the code DCO phase. By definition, the

pseudorange is expressed in time units and is equal to the

satellite-to-receiver propagation delay plus the user clock

bias. The user clock bias is first estimated (blind guessed

is more likely with a cold start, but iteration then takes

longer) and then obtained as a by-product of the navigation

solution. The pseudorange is equal to the user’s apparent

local time of reception of the signal (t1) minus the GPS

real time of transmission (t2).

With the demodulated data, the software has access to

the Space Vehicle Navigation Message, which contains

information on the GPS system time for the transmission

of the current sub-frame; this is equal to term t2.

The time information in the navigation message allows the

receiver time to be initialised with a resolution of 20

milliseconds (one data bit period) but with knowledge of

the precision to much better than one C/A code chip - a

little less than 1 microsecond. As the time-of-flight from

the satellite to the receiver is in the region of 60 to 80

milliseconds an improved first guess for local time could

GP2021

include an allowance for this delay to reduce the iteration

time later.

By using the data to time-tag the TIC, along with the values

of the Epoch counter, the Code generator phase, and the

Code clock phase it is possible to measure the time of the

SV signal in local apparent time. This gives the value of t1

needed for the pseudo-range measurement. The

pseudorange can now be computed as t12t2.

The error present in the time setting is the initial value of

the user clock bias, with an allowance for the various

counter phases. Once a Navigation Solution has been

found the clock error is precisely known and may be used

for future pseudorange calculations. Because the receiver

clock drifts with time, the clock bias changes with time and

must be tracked by the Navigation software.

CONTROLLING THE GP2021

The following section describes typical methods for

controlling the GP2021. These include signal acquisition

and tracking, carrier phase measurement and timemark

generation.

Search Operation

To perform signal acquistion, the carrier frequency and

code phase space needs to be searched until the signal is

detected. The maximum carrier frequency excursion from

its nominal value is defined by the maximum carrier Doppler

shift plus the maximum receiver clock error. The maximum

code phase is defined by the (fixed) code length. Typically,

all code phases will be searched at a given carrier

frequency before advancing to the next carrier frequency

bin and repeating the code phase search.

Carrier DCO Programming

The following registers:

CHx_CARRIER_DCO_INCR_HIGH

(or X_DCO _INCR_HIGH)

and CHx_CARRIER_DCO_INCR_LOW

are programmed in sequence with the relevant data

according to the frequency bin being searched. It is always

necessary to write to both the _HIGH and _LOW registers.

Carrier DCO programming will become effective as soon

as the channel is released (made active).

If the channel is already active, writes to

CHx_CARRIER_DCO_INCR_LOW are effective

immediately. (A short delay of up to 175ns will occur, to

allow synchronisation of the processor write operation to

the chip operation.)

Code DCO Programming

The following registers:

The CHx_CODE_DCO_INCR_HIGH

(or X_DCO_INCR_HIGH)

and CHx_CODE_DCO_INCR_LOW

are programmed in sequence with the relevant data

according to the estimated code frequency offset. It is

always necessary to write to both _HIGH and _LOW

registers. Code DCO programming will become effective

as soon as the channel is released (made active). If the

channel is already active, writes to

CHx_CODE_DCO_INCR_LOW are effective immediately.

(A short delay of up to 175ns will occur to allow

synchronisation of the processor write operation to the chip

operation).

Code Generator Programming

For each channel, the CHx_SATCNTL register is

programmed as follows:

1. Set the SOURCESEL bit to select the input signal

source.

2. Set the TRACK_SEL bits to set the Tracking arm code

to either early or late (with respect to the Prompt arm).

3. Set the G2_LOAD bits to select the required PRN code.

4. Program the CHx_CODE_SLEW register with the

desired code phase offset. The slew operation will

become effective upon CHx_RSTB release. The first

DUMP will generate accumulated data for the channel

and set the associated CHx_NEW_ACCUM_DATA

status bit.

5. Release the relevant CHx_RSTB bits of the

RESET_CONTROL register to make the channel active.

When the code clock is inhibited (to slew the code

phase) the Integrate and Dump module is held reset. It

will start to accumulate correlation results only after the

slew operation is completed.

A search for a satellite on more than one channel may be

performed using the MULTI channel addresses and

different code slew values as appropriate.

Reading the Accumulated Data

At each DUMP the corresponding

CHx_NEW_ACCUM_DATA status bit is set in the

ACCUM_STATUS_A register. The status register, together

with all accumulation registers (CHx_l_TRACK,

CHx_Q_TRACK, CHx_l_PROMPT, CHx_Q_PROMPT)

are mapped into consecutive addresses. These can be

read as a consecutive block, if required, after every

ACCUM_INT interrupt. Alternatively, the Status Registers

may be polled. The Accumulation registers are not

GP2021

overwrite protected, therefore the system must respond

quickly when new data becomes available. Whether or

not it is necessary to process the accumulation at every

DUMP is dependent upon the application. The order of

reading them is optional, but ideally the CHx_Q_PROMPT

CHx_NEW_ACCUM_DATA bit.

The CHx_MISSED_ACCUM bits in the

ACCUM_STATUS_B register indicate that new

accumulated data has been missed. These can only be

cleared by a write to CHx_ACCUM_RESET or by

deactivating the channel.

to instigate this operation. The reading of measurement

data can be either interrupt driven or polled. For the interrupt

driven method the microprocessor reads the

ACCUM_STATUS_B or MEAS_STATUS_A register after

each MEAS_INT, and if the TIC bit is set, subsequently

reads the Measurement data. For the polled method the

ACCUM_STATUS_A register is always read following

every ACCUM_INT. In addition the ACCUM_STATUS_B

Accumulated Data has been missed and to check the TIC

bit (along with several other status bits). The software tests

the TIC bit to determine if new Measurement Data is

available to be read.

Preset Mode

Each channel can be programmed into PRESET mode

by writing a High into the PRESET/UPDATEB bit of the

CHx_SATCNTL register.

When a TIC occurs, the satellite code, epoch value and

slew numbers are loaded, and a new phase programmed

into the Code DCO regardless of its previous value. Prior

to the TIC the channel operates with its previous settings.

Preset Mode has no effect on the Carrier DCO and Carrier

Cycle Counter.

If Preset mode is initiated, it should be allowed to operate

to completion. The required sequence of operations is as

follows:

1. Write into CHx_SATCNTL to select the PRESET mode,

together with the appropriate new settings.

2. Load the Code and Carrier DCO increment values.

Note: These will take effect immediately thereby

influencing the current measurements.

3. Load the following Registers:

CHx_CODE_DCO_PHASE, CHx_CODE_SLEW and

CHx_EPOCH_COUNT_LOAD. It is important that the

CHx_EPOCH_COUNT_LOAD occurs last, because it

enables the preset operation on the next TIC.

Interrupts

There are 2 interrupt sources: ACCUM_INT and

MEAS_INT. Their sense is dependent upon the selected

microprocessor interface mode. The default ACCUM_INT

period is 505·.05µs. However, it can be reconfigured via

the PROG_ACCUM_INT register or by changing the

INTERRUPT_PERIOD or FRONT_END_MODE bits in the

SYSTEM_SETUP register. The default MEAS_INT period

is 50ms. However, this can be reconfigured via the

PROG_TIC_HIGH and PROG_TIC_LOW registers.

Signal Path Delay Introduced by Hardware Signal

Processing

When it is desired to generate an accurate time reference

from GPS signals or to time-stamp position fixes the delays

in the receiver must be allowed for. The signal path delay

Search on Other Code Phases

When it is desired to correlate on the next code phase,

such as one whole chip later, the CODE_SLEW has to be

programmed with a value of 2 (the units are half code

chips). The slew will occur on the next DUMP. The effect

of CODE_SLEW is relative to the current code phase. To

repeat a CODE_SLEW, the register needs to be written to

again even if the same size slew is required.

Once the signal has been detected (correlation threshold

exceeded), the code and carrier tracking loops can be

closed. The tracking loop parameters must be tailored in

the software to suit the application.

Data Bit Synchronisation

The data bit synchronisation algorithm should find the data

bit transition instant. The processor calculates the present

one millisecond epoch and programs this value into the

1MS_EPOCH counter. Ideally, epoch counter accesses

should occur following the reading of the accumulation

Alternatively, the epoch counters can be left free-running

and the offset can be added by the software each time it

reads the epoch registers. Note that if the integration is

performed across bit boundaries, the integration result can

be very small.

Reading the Measurement Data

At each TIC, the measurement data is latched in the

Measurement Data registers:

CHx_EPOCH,

CHx_CODE_PHASE,

CHx_CARRIER_DCO_PHASE,

CHx_CARRIER_CYCLE_HIGH,

CHx_CARRIER_CYCLE_LOW,

CHx_CODE_DCO_PHASE.

The ACCUM_STATUS_B or MEAS_STATUS_A register

must be polled at a rate greater than the TIC rate (to see if

a TIC has occurred), otherwise measurement data will be

lost. The ACCUM_INT or MEAS_INT events can be used

GP2021

has two components, an analog path delay which varies

with temperature and component tolerances and a Digital

path delay which is constant if oscillator drift variations are

neglected.

The digital delay is easier to estimate and is made up of

the following:

In Real_lnput mode:

1. The time from the sampling edge of the SIGN and MAG

bits in the front end (SAMPCLK) to the re-sampling in

the Sample Latch (175ns less the propagation delay of

SAMPCLK to the Front-end).

2. Plus the time for the correlation in the Correlator on

these same SIGN and MAG bits (125 ns).

3. Plus the delay in the accumulator to latch the sampled

data (175 ns ).

4. Less the time between the correlation and the TIC clock

phase which is before the accumulator latch phase (75

ns), Giving a total of 400 ns less the SAMPCLK delay.

In Complex_lnput mode:

1. The time for the correlation in the Correlator on the S IGN

and MAG bits after sampling (114 ns).

2. Plus the delay in the accumulator to latch the sampled

data (171ns).

3. Less the time between the correlation and the TIC clock

phase which is before the accumulator latch phase

(86ns), giving a total of 199ns.

The analog delay through the radio receiver is set by such

parameters as group delay in filters, which for the

bandwidths used for C/A code will be in the region of

1 to 2ms and so swamps the digital delay, but this can be

measured and corrected for.

Integrated Carrier Phase Measurement

The Correlator tracking channel hardware allows

measurement of integrated carrier phase through the

CHx_CARRIER_CYCLE_HIGH and _LOW and the

CHx_CARRIER_DCO_PHASE registers, which are part

of the Measurement Data sampled at every TIC. The

CHx_CARRIER_CYCLE_HIGH and _LOW registers

contain the 20-bit number of positive-going zero crossings

of the Carrier DCO; this will be one more than the number

of full cycles elapsed (4 bits are in _HIGH and 16 in _LOW

contains the cycle fraction or phase, with 10-bit resolution

to give 2p/1024 radian increments.

To get the Integrated Carrier Phase over several TIC

periods all that is needed is to read the

CHx_CARRIER_CYCLE_HIGH and _LOW registers at

every TIC and sum the readings. This gives a number

1 higher than the number of complete carrier cycles, when

a carrier cycle is measured from one positive-going zero

crossing to the next.

To this number, the fractional carrier cycle at the end has

to be added, and the fractional carrier cycle at the beginning

has to be subtracted. Both numbers are read from the

CHx_CARR_DCO_PHASE register. The total phase

change can be calculated as follows:

Integrated Carrier Phase =

2p3S Numbers in Carrier Cycle Counter

1final Carrier DCO phase

2Initial Carrier DCO phase

Fig. 22 shows how this equation is derived.

This Integrated Carrier Phase may be related to the delta-

range (the change in distance to each satellite). When used

with the orbital parameters of the satellites, the delta ranges

give a measure of the receiver’s movement between fixes,

which is independent of those fixes and so can be used to

smooth them. It can also give a velocity directly. The delta

ranges will be noisy and most of the value is due to satellite

movement so the determination of velocity must use data

from adequately separated TlCs. For position smoothing

all delta ranges may be included in the input to the

navigation filter, as that filter will perform a running average

of the delta-ranges as well as the ranges.

Timemark Generation

The GP2021 is capable of generating an accurate

TIMEMARK timing output on one of the discrete outputs if

required. TIMEMARK is intended to be a UTC aligned

timing output with an accurate 1 second period and a pulse

width of 1 ms. The TIMEMARK output is always derived

from a rising edge on TIC, and for UTC aligned operation

the TIC counter must be brought into phase with UTC.

This is done by modifying the division ratio of the TIC

counter for a single TIC period by increasing or reducing

the division ratio, thus slewing the phase of TlC. Since the

TIC counter is incremented every 175ns which is not an

exact sub-multiple of 1 second it is also necessary to

continually monitor the relationship between TIC and UTC

to keep TIC in phase with UTC. Once TIC is in phase with

UTC, the TIMEMARK output can be derived from TIC using

one of 2 methods both of which involves writing to

TIMEMARK_CONTROL:

1. The GP2021 can be armed to produce a TIMEMARK

output at the next TIC only, or

2. It can be programmed to give a TIMEMARK output every

n TlCs starting at the next TIC.

A separate counter resets the TIMEMARK output giving a

1 ms pulse width. The TIC counter can be programmed

with an accuracy of 175ns in Real_lnput mode or 171.4ns

in Complex_lnput mode. This determines the accuracy of

the TIMEMARK output. If the TIC is continually

synchronised to keep the rising edge as close as possible

GP2021

to UTC, the internal TIMEMARK will be within 100ns

(4/73175ns) of UTC in Real_lnput mode or 85·7ns

(3/63171.4ns) of UTC in Complex_lnput mode. In addition,

there may be a delay of up to 50ns in getting the

TIMEMARK output off chip, giving a maximum error of

150ns (Real_lnput) or 135·7ns (Complex_lnput) between

TIMEMARK and UTC. It should be noted that due to the

need to re-synchronise TIC, a jitter of up to 175ns may be

present on TIMEMARK, along with any jitter and drift

present on the input clock. The pulse width of TIMEMARK

(in seconds) is either (571412/7)3(7/ Master Clock

Frequency) for Real_lnput mode giving 1·0000000ms

(assuming an accurate 40MHz master clock input) or

(583311/6)3(6/Master Clock Frequency) for

Complex_lnput mode giving 0·9999714ms (assuming an

accurate 35MHz master clock input).

PH0K1 CYCLES PH1K2 CYCLES PH2

DY1DY2

TIC0TIC1TIC2

1. Reading at TIC0: CHx_CARR_DCO_PHASE0 = PH0

2. Reading at TIC1 : CHx_CARR_DCO_PHASE1= PH1

CHx_CARR_CYCLE1 = K111

3. Reading at TIC2: CHX-CARR-DCO-PHASE2 = PH2

CHx_CARR_CYCLE2 = K211

DY1= 2pK11(2p2PH0)1PH1

= 2p(K111)2PH01PH1

= 2p(CHx_CARR_CYCLE12CHx_CARR_DCO_PHASE0/10241CHx_CARR_DCO_PHASE1/1024)

SDY= 2pS CHx_CARR_CYCLE12 CHx_CARR_DCO_PHASE0/10242CHx CARR_DCO_PHASELAST/1024)

Note: The Carrier Cycle Counter value is stored at every TIC and the Counter is reset

Figure 22 Integrated carrier phase

LAST

i = 1

GP2021

Correlator

CNTL

ACCUM

000 to 01C

020 to 03C

040 to 05C

060 to 07C

080 to 09C

0A0 to 0BC

0C0 to 0DC

0E0 to 0FC

100 to 11C

120 to 13C

140 to 15C

160 to 05C

180 to 19C

1A4

1AC

1B4

1BC

1C0 to 1DC

1EC

1F0

1F4

1F8

1FC

200 to 20C

210 to 21C

220 to 22C

230 to 23C

240 to 24C

260 to 26C

270 to 27C

280 to 28C

290 to 29C

2A0 to 2AC

2B0 to 2BC

2C0 to 2BC

2D0 to 2DC

2E0 to 2EC

00 to 07

08 to oF

10 to 17

18 to 1F

20 to 27

28 to 2F

30 to 37

38 to 3F

40 to 47

48 to 4F

50 to 57

58 to 5F

60 to 67

70 to 77

80 to 83

84 to 87

88 to 8B

8C to 8F

90 to 93

98 to 9B

9C to 9F

A0 to A3

A4 to A7

A8 to AB

AC to AF

B0 to B3

B4 to B7

B8 to BB

CH0 Control

CH1 Control

CH2 Control

CH3 Control

CH4 Control

CH5 Control

CH6 Control

CH7 Control

CH8 Control

CH9 Control

CH10 Control

CH11 Control

MULTI Control

X_DCO_INCR_HIGH

PROG_ACCUM_INT

PROG_TIC_HIGH

PROG_TIC_LOW

ALL Control

TIMEMARK_CONTROL

TEST_CONTROL

MULTI_CHANNEL_SELECT

SYSTEM_SETUP

RESET_CONTROL

Status Registers

CH0 Accumulate

CH1 Accumulate

CH2 Accumulate

CH3 Accumulate

CH5 Accumulate

CH6 Accumulate

CH7 Accumulate

CH8 Accumulate

CH9 Accumulate

CH10 Accumulate

CH11 Accumulate

MULTI Accumulate

ALL Accumulate

A<22:20> A<9:0> A<9:2>

Arm

system

mode

Standard

interface

mode

Address (Hex)

block Registers

DETAILED DESCRIPTION OF REGISTERS

GP2021 Register Map

The register map of the GP2021 is shown in Table 11. The

addresses are complete, and it should be noted that all the

used. Adjacent register addresses thus increment by 4, in

ARM System Mode. However, in Standard Interface Mode,

the GP2021 address lines A<9:2> could be connected to the

processor address lines A<7:0>. Note that in this mode pins

A0 and A1 are allocated other functions.

Table 11 Register map Cont…

GP2021

Real Time Clock

DUART

System control

General control

000

004

008

00C

010

040

044

048

04C

050

054

058

05C

080

084

088

08C

090

0C0

0C4

0C8

A<22:20> A<9:0> A<9:2>

Arm

system

mode

Standard

interface

mode

Address (Hex)

block Registers

RTC_LS

RTC_2ND

RTC_MS

CLOCK_RESET

WATCHDOG_RESET

TX_DATA_A, RX_DATA_A

TX_DATA_B, RX_DATA_B

CONFIG_A, STATUS_A

CONFIG B, STATUS_B

CH10 Control

CH11 Control

MULTI Control

X_DCO_INCR_HIGH

WAIT_STATE

SYSTEM_CONFIG

Not Used

SYSTEM_ERROR_STATUS

DATA_RETENT

IO_CONFIG

TEST_CONFIG

DATA BUS TEST

Table 11 Register map (continued)

GP2021

ACCUM_STATUS_C

MEAS_STATUS_A

ACCUM_STATUS_A

ACCUM_STATUS_B

Arm

system

mode

Standard

interface

mode

Address (Hex)

CNTL 100

CNTL 104

CNTL 108

CNTL 10C

CNTL 110

CNTL 114

CNTL 118

CNTL 11C

ACCUM100

ACCUM104

ACCUM108

ACCUM10C

Write function

CNTL 10

CNTL 11

CNTL 12

CNTL 13

CNTL 14

CNTL 15

CNTL 16

CNTL 17

ACCUM10

ACCUM11

ACCUM12

ACCUM13

SATCNTL

CODE PHASE COUNTER (1)

CARRIER_CYCLE_COUNTER (1)

CARRIER_DCO_INCR_HIGH

CARRIER DCO_INCR_LOW

CODE_DCO_INCR_HIGH

CODE_DCO_INCR_LOW

EPOCH_COU NT_LOAD

CODE_SLEW_COUNTER

ACCUM_RESET

Not used

CODE_DCO_PRESET_PHASE

CODE_SLEW

CODE_PHASE

CARRIER_CYCLE_LOW

CARRIER_DCO_PHASE

EPOCH (Latched 0)

CODE_DCO_PHASE

CARRIER_CYCLE_HIGH

EPOCH_CHECK (Not latched)

I_TRACK

Q_TRACK

l_PROMPT

Q_PROMPT

Read function

NOTES

1. The CODE_PHASE_COUNTER and CARRIER_CYCLE_CONTROL registers can only be written to if Test mode

has been selected by setting bit 3 of the TEST CONTROL register high.

Table 12 Tracking channel registers

Arm

system

mode

Standard

interface

mode

Address (Hex)

200

204

208

20C

Write function

Read function

STATUS

Not used

Table 13

Correlator Registers

Addresses for the Correlator Registers may be calculated

from a base address with an increment for a particular

The base addresses for the CNTL and ACCUM register

blocks for each channel in the Correlator are shown in

Table 11, the increments being given in Table 2.

For example, in ARM System Write mode:

CH3_CODE_DCO_INCR_LOW = 060H1018H = 078H.

In both the ACCUM and CNTL sections there are some

addresses labelled ALL or MULTI in place of CHx. Writing

to these addresses will write to all channels or to a selection

set by MULTI_CHANNEL_SELECT in one operation and

so may be used to initialise the system quickly or to load

the next search settings with little bus use. This is a write-

only function and the corresponding CHx read functions

are not available at addresses labelled ALL or MULTI.

It can be seen that the addresses in CNTL are used to

control the device in write mode but give the Measurement

Data when in read mode.

Apart from the Code and Carrier DCO increment values

all data transfers are only 16-bit wide. Writes to the Code

and Carrier DCOs are 32-bit data transfers where

the_HIGH word should be written first and will be retained

in the 16- to 32-bit interface until the _LOW word is written,

which must occur as the next write to the chip. All 32 bits

will then be transferred into the DCO increment register.

Data is written to an input buffer in the 16- to 32- bit interface

and will be transferred to its destination register during the

next full cycle of the 7 (or 6) phase clock. Write cycles

should therefore have a period of at least 300 ns. The

X_DCO_INCR_HIGH may be used to write the high bits

of the increment number to any or all DCO’s as an

alternative to using the CHx_CODE

CARRIER_DCO_INCR_HIGH addresses. By using this

GP2021

address, there is no need to wait 300ns before writing the

_LOW part. For further information refer to General

Interface Timing in Microprocessor Interface section.

The bit assignments for the Correlator registers are given

below, but two write-only registers do not have any data

bits, these are:

1. A write to the CHx_ACCUM_RESET register

(irrespective of what data is written) will reset the

ACCUM_STATUS_A, ACCUM_STATUS_B, and

ACCUM_STATUS_C registers for that channel.

2. A write to the STATUS register (irrespective of what

data is written) will latch the state of the various status

flags into ACCUM_STATUS_A, ACCUM_STATUS_B

and ACCUM_STATUS_C Registers for all channels.

This allows a polling based rather than Interrupt driven

tracking scheme.

The registers are listed in alphabetical order and not in

address order to allow easy reference to each section.

Unless otherwise stated the LSB is bit 0 and the MSB is

bit 15 or as far up the register as there is data. Note that

most registers do not have both read and write functions,

and many addresses are shared between read-only and

write-only registers having different functions.

ACCUM_STATUS_A (Read address)

ACCUM_INT

Not used-low

CH11_NEW_ACCUM_DATA

CH10_NEW_ACCUM_DATA

CH9_NEW_ACCUM_DATA

CH8_N EW_ACCU M_DATA

CH7_NEW ACCUM_DATA

CH6_NEW_ACCUM_DATA

CH5_NEW ACCUM_DATA

CH4_NEW_ACCUM_DATA

CH3_NEW_ACCUM_DATA

CH2_NEW_ACCUM_DATA

CH1_NEW_ACCUM_DATA

CH0_NEW_ACCUM_DATA

Bit nameBit

The ACCUM_INT bit is set high at every ACCUM_INT

and is reset by reading the ACCUM_STATUS_A register.

This status bit is reset by a hardware master reset but not

by a software reset (MRB).

The CHx_NEW_ACCUM_DATA status bit indicates that

a DUMP has occurred in that channel, and that new

Accumulated Data is available to be read.

Each bit is cleared by the trailing edge of a read of the

associated CHx_Q_PROMPT register or by a write to

CHx_ACCUM_RESET. Note that the channel-specific bits

of this register will not show their new value until after an

active edge of ACCUM_INT or a write to the STATUS

immediately.

ACCUM_STATUS_B (Read address)

Bit name

Bit

DISCIP_GLITCH

DISCIP

TIC

MEAS_I NT

CH1 1_MISSED ACCUM

CH10_MISSED_ACCUM

CH9_MISSED_ACCUM

CH8_MISSED_ACCUM

CH7_MISSED_ACCUM

CH6_MISSED_ACCUM

CH5_MiSSED_ACCUM

CH4_MISSED_ACCUM

CH3_MISSED_ACCUM

CH2_MISSED_ACCUM

CH1_MISSED ACCUM

CH0_MISSED_ACCUM

The lower 12 bits of ACCUM_STATUS_B bits are sampled

and latched on the active edge of every ACCUM_INT

signal. They can be sampled and latched on request by

performing a write operation to STATUS (as with

ACCUM_STATUS A).

The DISCIP_GLITCH bit will be set high if a glitch-to-low

has occurred on the DISCIP pin since the last read of this

(NRESET at low) but not by a software reset (MRB). The

minimum reliably detectable glitch width is 25ns.

The DISCIP bit indicates the level on the DISCIP input

pin at the time this read occurs and may be used to interface

a hardware condition (such as a ready flag from a UART

or the PLL LOCK signal from a front end) to the

microprocessor without using an interrupt. This bit is not

reset by a hardware master reset nor by an MRB.

Table 15

ACCUM_STATUS_A is a register containing the state of

twelve status bits sampled and latched on the active edge

of every ACCUM_INT. They can also be sampled and

latched on request, by performing a write operation to

STATUS. (This is safe only if the interrupts are stopped,

by setting INTERRUPT_ENABLE bit to low in the

SYSTEM_SETUP register.) The microprocessor must

respond to each ACCUM_INT and read the channel

registers before the next DUMP is due in that channel.

Table 14

GP2021

The TIC bit is set High at every TIC and is cleared by

reading this ACCUM_STATUS_B register. Its purpose is

to tell the microprocessor that new Measurement Data is

available. It is reset by a hardware master reset (NRESET

at low) but not by an MRB in RESET_CONTROL.

Provided that interrupts are enabled, the MEAS_INT bit is

set High at each TIC and 50ms before each TIC if the TIC

period is greater then 50ms), and is cleared by reading

this register. This bit can be used as a flag to the

microprocessor, to time software module swapping. It is

reset by a hardware master reset (NRESET at low), but

not by a software reset. CHx_MISSED_ACCUM status bit

indicates (when high) that there has been missed

Accumulated Data due to a new DUMP in CHx before the

previous data has been read. This bit is latched until the

associated CHx_ACCUM_RESET is written to. If any data

is missed due to the reading process being too slow this

must be allowed for in the software, such as by checking

the Navigation Message data bit transitions independently

of the sets of Accumulated Data reads. If too much data is

lost the system signal to noise ratio will be degraded. The

primary purpose of these bits is as a check on how well

the tracking routines are working - once the whole design

is complete these bits should not become set.

Note that the channel-specific bits of this register will not

show their new value until after an active edge of

ACCUM_INT or a write to the STATUS register. Disabling

a channel will however, clear the bit immediately.

ACCUM_STATUS_C (Read address)

Bit nameBit

Table 16

Not used - low

CH11_EARLY_LATEB

CH10_EARLY_LATEB

CH9_EARLY_LATEB

CH8_EARLY_LATEB

CH7_EARLY_LATEB

CH6_EARLY_LATEB

CH5_EARLY_LATEB

CH4_EARLY_LATEB

CH3_EARLY_LATEB

CH2_EARLY_LATEB

CH1_EARLY_LATEB

CH0_EARLY_LATEB

ACCUM_STATUS_C bits are sampled and latched on the

active edge of every ACCUM_INT signal, or they can be

sampled and latched on request by performing a write

operation to STATUS (as with ACCUM_STATUS A).

The CHx_EARLY_LATEB status bit indicates the code

type for the Accumulated Data on the Tracking arm of

channel CHx when that channel is in Dithering mode. A

high indicates an EARLY code and a low indicates a LATE

code. Each individual bit is determined on the DUMP that

sets CHx_NEW_ACCUM_DATA to high for that channel.

In other modes the bit is of no use.

Note that the channel specific bits of this register will not

show their new value until after an active edge of

ACCUM_INT or a write to the STATUS register. Disabling

a channel will however, clear the bit immediately.

CHx_ACCUM_RESET (Write Address)

Bits 15 to 0: Not used.

These are write-only locations provided to allow resetting

of the status bits ACCUM_STATUS_A,

ACCUM_STATUS_B, and ACCUM_STATUS_C

associated with a given channel or all channels. When

these locations are written to, the data is irrelevant.

CHx_CARRIER_CYCLE_COUNTER,

MULTI_CARRIER_CYCLE_COUNTER,

ALL _CARRIER_CYCLE_COUNTER

(Write Address)

A write to these registers only has effect when in test mode

(bit 3 of TEST_CONTROL set high). The value on the bus

is loaded into the lower 16 bits of the

CHx_CARRIER_CYCLE_COUNTER along with zeros into

the upper 4 bits.

CHx_CARRIER_CYCLE_HIGH,

CHx_CARRIER_CYCLE_LOW

(Read Address)

_HIGH bits 15 to 4: not used - low when read.

_HIGH bits 3 to 0: Carrier Cycle Count bits 19 to 16.

_LOW bits 15 to 0: Carrier Cycle Count bits 15 to 0.

The Correlator tracking channel hardware allows for

measurement of integrated carrier phase through the

CHx_CARRIER_CYCLE_HIGH and _LOW and the

CHx_CARRIER_DCO_PHASE registers, which are part

of the Measurement Data sampled at every TIC. The

CHx_CARRIER_CYCLE_HIGH and _LOW registers

contain the 20- bit number of positive going zero crossings

of the Carrier DCO (4 bits are in _HIGH and 16 in _LOW).

GP2021

The cycle fraction can be read from the

CHx_Carrier_DCO_Phase register.

In the CHx_CARRIER_CYCLE counter, a TIC generates

two consecutive actions. First it latches the 4 more

significant bits of the cycle counter into

CHx_CARRIER_CYCLE_HIGH and the 16 less significant

bits into CHx_CARRIER_CYCLE_LOW. Then it resets the

cycle counter.

After each TIC, every time the Carrier DCO accumulator

generates an overflow as a result of a carrier cycle being

completed, the cycle counter increments by one.

In Real_lnput mode the nominal CARRIER DCO frequency

with no Doppler and no oscillator drift compensation is

1·405396825 MHz, so in 100ms, there will be about 140540

cycles.

In almost all applications the number of Carrier DCO cycles

does not vary much from one TIC interval to another so it

is possible to predict the Most Significant Bits of the value

and then only read the CHx_CARRIER_CYCLE_LOW

CHx_CARRIER_CYCLE_HIGH and_LOWcontents are

not protected by an overwrite protection mechanism and

so must be read before the next TIC.

For further information on the Carrier Cycle Counter refer

to The Tracking Modules section on page 8.

CHx_CARRIER_DCO_INCR_HIGH,

X_DCO_INCR_HIGH,

MULTI_CARRIER_DCO_INCR_HIGH,

ALL_CARRIER_DCO_INCR_HIGH,

CHx_CARRIER_DCO_INCR_LOW,

MULTI_CARRIER_DCO_INCR_LOW,

ALL_CARRIER_DCO_INCR_LOW

(Write Address)

_INCR_HIGH bits 15 to 10: Not used in this operation.

_INCR_HIGH bits 9 to 0: More significant bits (25 to 16)

of the Carrier DCO phase increment when used before a

write to _CARRIER_DCO_INCR_LOW.

_INCR_LOW bits 15 to 0: Less significant bits (15 to 0) of

the Carrier_DCO (phase increment.

The contents of registers _INCR_HIGH and_lNCR_LOW

are combined to form the 26 bits of the

CHx_C,ARRIER_DCO_INCR register, the carrier DCO

phase increment number. In order to write successfully,

the top 10 bits must be written first, to any of the _HIGH

addresses. They will be stored in a buffer and only be

transferred into the increment register of the DCO together

with the _LOW word. A 26-bit increment number is

adequate for a 27-bit accumulator DCO, as the increment

to the MSB is always zero.

The LSB of the INCR register represents a step given by:

Min. step frequency, Real_Input mode = (40MHz47)4227

= 42·57475mHz

Min. step frequency, Complex_Input mode = (35MHz46)4227

= 43·46172mHz

Output frequency = CHx_CARRIER_DCO_INCR (min. step

frequency).

With a GP2015/GP2010 style front end, the nominal value

of the IF is 1·405396826 MHz before allowing for Doppler

shift or crystal error. Writing 01F7B1B9H into the

CHx_CARRIER_DCO_INCR register will generate a local

oscillator frequency of 1·405396845 MHz.

CHx_CARRIER_DCO_PHASE (Read Address)

Bits 15 to 10: Not used - low when read.

Bits 9 to 0: More significant bits (26 to 17) of

CHx_CARRIER_DCO_PHASE as sampled at the last TIC.

The weight of the least significant bit is 2p/1024 radians of

a Carrier DCO cycle. These bits form an unsigned integer

valid from 0 to 1023. CHx_CARRIER_DCO_PHASE

provides sub-cycle phase measurement information and

so complements the information given by

CHx_CARRIER_CYCLE_HIGH and_LOW.

The register value is latched on each TIC and is not

protected by any overwrite protection mechanism.

CHx_CODE_DCO_INCR_HIGH,

X_DCO_INCR_HIGH,

MULTI_CODE_DCO_INCR_HIGH,

ALL_CODE_DCO_INCR_HIGH,

CHx_CODE_DCO_INCR_LOW,

MULTI_CODE_DCO_INCR_LOW,

ALL_CODE_DCO_INCR_LOW

(Write Address)

_INCR_HIGH bits 15 to 9: Not used in this operation.

_INCR_HIGH bits 8 to 0: More significant bits (24 to 16)

of the Code DCO phase increment when used before a

CODE_DCO_INCR_LOW.

_INCR_LOW bits 15 to 0: Less significant bits (15 to 0) of

the Code DCO phase increment.

The contents of registers _INCR_HIGH and _INCR_LOW

are combined to form the 25 bits of the

CHx_CODE_DCO_INCR register, the Code DCO phase

increment number. In order to write successfully, the top

9 bits must be written first, to any of the _HIGH addresses.

They will be stored in a buffer and only be transferred into

the increment register of the DCO together with the _LOW

GP2021

word. A 25-bit increment number is adequate for a 26-bit

accumulator DCO as the increment to the MSB is always

zero.

The LSB of the INCR register represents a step given by:

Min. step frequency, Real_Input mode = (40MHz47)4226

= 85·14949mHz

Min. step frequency, Complex_Input mode = (35MHz46)4226

= 86·92344mHz

Output frequency = CHx_CARRIER_DCO_INCR (min. step

frequency).

Note: The Code DCO drives the Code Generator to give

half chip time steps and so must be programmed to twice

the required chip rate. This means that the chip rate

resolution is 42·57475mHz in Real_lnput mode or

43·46172mHz in Complex_Input mode.

The nominal frequency is 1.023000000MHz before

allowing for Doppler shift or crystal error. Writing

016EA4A8H into the CHx_CODE_DCO_INCR register will

generate a chip rate of 1.022999968MHz in Real_lnput

mode. In Complex_mode, 01672922H will generate a chip

rate of 1.022999970 MHz.

CHx_CODE_DCO_PHASE (Read Address)

Bits 15 to 10: Not used (low when read).

Bits 9 to 0: CHx_CODE_DCO_PHASE: Contains the ten

more significant bits (25 to 16) of the Code DCO phase

accumulator sampled at a TIC event. It is an unsigned

integer valid from 0 to 1023. The weight of the least

significant bit is 2p/1024 radians, 2p being half of a code

chip, so the pseudorange resolution is 1/2048 of a chip,

(equivalent to 0·15 metre or 0·5ns).

The CHx_CODE_DCO_PHASE content is not protected

by any overwrite protection mechanism.

CHx_CODE_DCO_PRESET_PHASE,

MULTI_CODE_DCO_PRESET_PHASE,

ALL_CODE_DCO_PRESET_PHASE

(Write Address)

Bits 15 to 8: Not used.

Bits 7 to 0: More significant bits (25 to 18) of the Code

DCO phase which is to be loaded at the next TIC event in

PRESET mode.

In PRESET mode, the 8 bits of the CHx_CODE

_DCO_PRESET_PHASE register, with zeros filling the

lower bits, are transferred to the CODE DCO accumulator

on the next TIC. The previous accumulator phase is totally

overwritten. The PRESET_PHASE register is a write-only

mode or in UPDATE mode, but only has effect when

PRESET mode is entered. The weight of the least

significant bit of PRESET phase is 2p/256 radians of a

half chip cycle.

In UPDATE mode this register has no use other than as

preparation for PRESET mode.

Refer to Detailed Operation of GP2021 for further

information on PRESET mode, page 25.

CHx_CODE_PHASE (Read Address)

CHx_CODE_PHASE_COUNTER,

MULTI_6ODE_PHASE_COUNTER,

ALL_CODE_PHASE_COUNTER

(Write Address)

Bits 15 to 11: Not used, Low when read.

Bits 10 to 0: CHx_CODE_PHASE (Read) This is the state

of the Code Phase Counter, (an 11-bit binary up counter

clocked by the Code Generator Clock), stored on TIC. The

phase is expressed as a number of half code chips and

ranges from 0 to 2046 half chips. A reading of 2046 is very

rare and can only occur if the TIC captures the Code phase

just after the counter reaches 2046 and before it is reset

by a DUMP from the C/A Code Generator. DUMP also

increments the Epoch counter, so the meaning of a phase

value of 2046 1 the previous Epoch value is the same as

a phase value of 0 1 the incremented Epoch value, and

either is valid. If a TIC occurs during a Code Slew the

reading will be 0, and that channel’s Measurement Data is

of no use.

Bits 10 to 0: (Write) loads the 11 bits of the

CHx_CODE_PHASE_COUNTER. A write to these

registers is only possible in test mode, enabled by setting

the TM_TEST bit of TEST_CONTROL to High.

CHx_CODE_SLEW (Read Address)

CHx_CODE_SLEW_COUNTER,

MULTI_CODE_SLEW_COUNTER,

ALL_CODE_SLEW_COUNTER

(Write Address)

Bits 15 to 11: Not used.

Bits 10 to 0: An unsigned integer ranging from 0 to 2047

representing the number of code half chips to be slewed

immediately after the next DUMP if in UPDATE mode

orafter the next TIC, if in PRESET mode. Since there are

only 2046 half chips in a GPS C/A code, a programmed

value of 2047 is equivalent to a programmed value of 1,

but the next DUMP event will take place 1ms later. In

PRESET mode, the slew timing is set only by TIC, which

will also reset the code generator, (no DUMP is needed).

A non-zero slew must always be programmed when using

PRESET mode.

GP2021

The CHx_CODE_SLEW register can be written to at any

time. If two accesses have taken place before a DUMP in

U PDATE mode or before a TIC when in PRESET mode,

the latest value will be used at the next slew operation.

During the time a slew process is being executed, any

further write access to the CHx_CODE_SLEW register will

be stored until the following DUMP and then cause the

transfer of this new value into the counter. This situation

may be avoided by synchronising the access with the

associated CHx_NEW_ACCUM_DATA status bit.

If a channel is inactive, a non-zero slew value should be

written into CHx_CODE_SLEW before the channel is

released. This write will be acted on immediately the reset

is released.

If a TIC occurs during or soon after a slew the channel will

not be locked to the satellite, so the Measurement Data

for that channel will not be of use.

The ability to read the Slew counter is included only for

testing hardware or software and has no other use. It will

only give a non-zero result if the read occurs during the

actual slew operation. An example of a slewing event is

shown in Fig.23.

1021 1022 1023 1 1 1 1 2 3

DUMPDUMP DUMP

1023 CHIPS 1025·5 CHIPS

C/A CODE CHIP NO:

t1: Load 5 into CHx_CODE_SLEW register = 2·5 chips delay

TIME

Figure 23 Slew timing in UPDATE mode

CHx_EPOCH_CHECK (Read Address)

Bits 15 to 14: Not used.

Bits 13 to 8: Instantaneous value of CHx_20MS_EPOCH.

Bits 7 to 5: Not used.

Bits 4 to 0: Instantaneous value of CHx_1MS_EPOCH.

Reading this address gives the instantaneous value of the

CHx_1MS_EPOCH and the CHx_20MS_EPOCH

counters. It can be used to verify if the Epoch counters

have been properly initialised by the software. Its value is

not latched and is incremented on each DUMP. To ensure

the correct result, this register should be read only when

there is no possibility of getting a DUMP during the read

cycle, by synchronising the read to NEW_ACCUM_DATA.

The ranges of these values are the same as those seen in

the CHx_EPOCH register.

CHx_EPOCH (Read Address)

Bits 15, 14, 7, 6 and 5: Not used. Read gives low.

Bits 13 to 8: CHx_20MS_EPOCH The 20ms epoch

counter value that was sampled at the last TIC event, with

a valid range from 0 to 49.

Bits4 to 0: CHx_1 MS_EPOCH The 1ms epoch counter

CHx_EPOCH_COUNT_LOAD

MULTI_EPOCH_COUNT_LOAD

ALL_EPOCH_COUNT_LOAD

(Write Address)

Bits 15, 14, 7, 6, and 5: Not used.

Bits 13 to 8: CHx_20MS_EPOCH The value to be loaded

into the 20 millisecond epoch counter, with a valid range

from 0 to 49.

Bits 4to 0: CHx_1 MS_EPOCH Thevalue to be loaded

intothe 1 millisecond epoch counter, with a valid range from

0 to 19. This operation is affected by the current channel

mode, (PRESET or UPDATE). In UPDATE mode, the data

written into these registers is immediately transferred to

the 1ms and 20ms epoch counters. In PRESET mode

however, the data is transferred only after the next TIC.

It is important to load the CHx_EPOCH register last in the

PRESET mode loading sequence because the trailing

edge of a write to this register enables the whole PRESET

operation on the next TIC.

Refer to Detailed Operation of the GP2021 for more details

of the PRESET mode on page 25

value that was sampled at the last TIC event, with a valid

range from 0 to 19.

GP2021

CHx_l_TRACK,

CHx_Q_TRACK,

CHx_l_PROMPT,

CHx_Q_PROMPT

(Read Address)

Bits 15 to 0: Accumulated Data registers, which are used

on each DUMP to store the 16-bit Integrate-and-Dump

accumulator results. The values contained in the registers

are 2’s complement values with the valid range of the data

from 2215 to 1(21521)

These registers are read-only registers which can be read

at any time. Their content is not protected by any overwrite

protection mechanism, so the set of four registers must be

read soon after an ACCUM_INT to be sure that newer

data will not cause an overwrite part way through the set.

The CHx_l_PROMPT and CHx_Q_PROMPT contain the

Accumulated Data from the Prompt arm. The

CHx_l_TRACK and CHx_Q_TRACK contain the

Accumulated Data from the Tracking arm.

To track satellites correctly, only data read with the

CHx_NEW_ACCUM_DATA bit set High should be used.

An overflow or underflow condition cannot be reached.

CHx_SATCNTL,

MULTI_ SATCNTL,

ALL_SATCNTL

(Write Address)

Bit name

Bit

GPS_NGLON

TRACK_SEL

PRESET/UPDATEB

CODE_OFF/ONB

SOURCESEL

G2_LOAD (9 to 0)

Table 17

CHx_SATCNTL is a write-only register that can be written

into at any time. Any modification to the content is effective

at the next DUMP in UPDATE mode or at the next TIC in

PRESET mode for all bits, apart from PRESET/UPDATEB,

which defines whether a channel is in PRESET or UPDATE

mode. It is important to program this register first when

starting the initialisation of a PRESET sequence to get the

channe linto PRESET mode, or the other write operations

will act too soon.

G2_LOAD (9 to 0), bits 9 to 0: C/A CODE SELECTION

FUNCTION: The CHx_SATCNTL register programs the

CODE GENERATOR by setting the G2 register to the

appropriate starting pattern to generate the required GPS

or INMARSAT-GIC codes. The G2_LOAD register may

be programmed at any time but the value is only used

when the code sequence restarts, at the following DUMP

in UPDATE mode, or at the following TIC in PRESET mode.

The pattern to load is the register state for the time of the

second code chip. The followinqtable shows the values

required to select one of the 37 GPS or the 8 INMARSAT-

GIC possible PRN (Pseudo Random Noise) patterns. In

UPDATE mode, the C/A code generated by the CODE

GENERATOR will be changed at the DUMP following the

write to CHx_SATCNTL and at this DUMP the Accumulated

Data will be valid for the previous code selection. Later

DUMPs will be valid for the new code.

If all zeros are loaded into the G2 register it will not clock

out, and the G1 generator code will be seen on the output.

This is an illegal state, which is only of use for chip testing.

Notes:

●PRN sequences 33 to 37 are reserved for non-satellite

uses (e.g. Ground transmitters - ‘Pseudo-Lites’)

●C/A codes 34 and 37 are equivalent.

●PRN sequences 120 to 138 are selected for the Wide

Area Augmentation System (WAAS).

●PRN sequences 201 to 211 are selected for INMARSAT

GIC (GPS Integrity Channel) use.

Due to the initialisation of the Early-Prompt-Late shift

of the sequence after a Code change or a Code Siew.

Subsequent cycles of the PRN sequence will be correct

for the chosen satellite.

GPS

PRN

signal

no.

3F6

3EC

3D8

3B0

04B

096

2CB

196

32C

3BA

374

1D0

3A0

340

280

100

113

226

04C

098

130

260

267

GPS

PRN

signal

no.

120

121

122

123

124

125

126

338

270

0E0

1C0

380

22B

056

0AC

158

2B0

058

18B

316

058

2C4

30A

1DA

0B2

3E3

0F8

25F

GPS

PRN

signal

no.

127

128

129

130

131

132

133

134

135

136

137

138

201GIC

202GIC

205GIC

206GIC

207GIC

208GIC

209GIC

211GIC

1E7

2B5

22A

10E

12D

215

337

0C7

0E2

20F

3C0

029

2C4

10A

3E3

0F8

25F

1E7

2B5

10E

G2_LOAD

[9:0]

(hex)

G2_LOAD

[9:0]

(hex)

G2_LOAD

[9:0]

(hex)

Table 18 G2_LOAD settings required for satellite reception

14-13

9-0

GP2021

SOURCESEL, bit 10: Selects which input source to be

used by the channel when in Real_lnput mode. Low selects

SIGN0 and MAG0, high selects SIGN1 and MAG1.

CODE_OFF/ONB, bit 11: When low, the code is output

normally, but when high, the Prompt, Early and Late codes

are held high (code mixer outputs exactly follow inputs)

and the Early-minus-late code is held low. This is intended

for test purposes only.

PRESET/UPDATEB, bit 12: When high sets the channel

into Preset mode, or when low, sets the channel into Update

mode. This bit is cleared to low after the Preset function

has been performed, that is, after the first TIC following

the loading of the Epoch counters.

TRACK_SEL (1 and 0), bits 14 and 13: Select the

appropriate code to be produced by the Tracking arm

output of the code generator as shown in Table 19.

Bit

14 Code select

Early code

Late code

Dithering code (alternating early and late)

Early-minus-late code

Table 19 TRACK_SEL bit settings for Tracking arm

code selection

When the dithering code has been selected, the Tracking

arm will use the Early code for 20 periods of the Gold code,

the Late code for the next 20 periods and then this process

of alternating between Early and Late code will be repeated

indefinitely. The Tracking Arm will toggle between Early or

Late codes on every increment of a 20ms Epoch Count.

Its state can be determined by reading the

ACCUM_STATUS_C register.

The output code is a sequence of 11s and 21s for all

code types except EARLY-MINUS-LATE where the result

can also be a 0. In EARLY-MINUS-LATE mode the values

are not the 12, 0, 22 that result from the calculation (11

or 21) 2 (11 or 21), but are halved to 11, 0, 21. This

must be considered when choosing thresholds in the

software as the correlation results will be exactly half the

values otherwise expected.

GPS_NGLON, bit 15: Setting this bit to low changes the

C/A code generator mode to GLONASS mode, to generate

the fixed 511-bit sequence used by all GLONASS satellites.

After a master reset (NRESET low), GPS mode is selected,

but with all zeros in the G2 generator, the G1 code is seen

at the output of the C/A code generator.

CHx_MISSED_MEAS_DATA status bit, when high,

indicates that one or more sets of measurement data have

been missed since the last read from this register. It is set

high by a read from the Code Phase Counter of the same

channel, when the previous value in the Code Phase

Counter has not been read, and is reset by a read from

the MEAS_STATUS_A register or by disabling the channel.

If this register is always read after the Code Phase Counter,

it indicates whether measurement data has been missed

before the last read of the Code Phase Counter. All

CHx_MISSED_MEAS_DATA bits are set low by a

hardware (NRESET) or software (MRB reset.

The MEAS_INT bit is set high at each TIC and 50ms before

each TIC (if TIC period is greater then 50ms), and is cleared

by reading this register. This bit is used as a flag to the

microprocessor to time software module swapping and is

reset by a hardware master reset (NRESET low) but not

by an MRB software reset.

The TIC bit is set high at every TIC and is cleared by

reading this register. The purpose of the bit is to tell the

microprocessor that new Measurement Data is available.

This bit is reset by a hardware master reset (NRESET at

low) but not by an MRB in RESET_CONTROL.

MEAS_STATUS_A (Read address)

Bit nameBit

Not used

TIC

MEAS_INT

CH11_MISSED_MEAS_DATA

CH10_MISSED_MEAS_DATA

CH9_MISSED_MEAS_DATA

CH8_MISSED_MEAS_DATA

CH7_MISSED_MEAS_DATA

CH6_MISSED_MEAS_DATA

CH5_MISSED_MEAS_DATA

CH4_MISSED_MEAS_DATA

CH3_MISSED_MEAS_DATA

CH2_MISSED_MEAS_DATA

CH1_MISSED_MEAS_DATA

CH0_MISSED_MEAS_DATA

15 to 14

Table 20

GP2021

MULTI_CHANNEL_SELECT (Write address)

Bit nameBit

15 to 12

Not used

CH11_SELECT

CH10_SELECT

CH9_SELECT

CH8_SELECT

CH7_SELECT

CH6_SELECT

CH5_SELECT

CH4_SELECT

CH3_SELECT

CH2_SELECT

CH1_SELECT

CH0_SELECT

SYSTEM_SETUP register to set the period of the

ACCUM_INT output. ACCUM_INT is generated by a 13-

bit binary down counter which counts down to zero,

producing an ACCUM_INT output. It then loads to a preset

value stored in its preset register and starts to count down

again. If the preset value is P, the count sequence is P,

P21, P22, ..., 1, 0, P, P21. Hence, the counter divides by

P11, producing an output with a period of (P11) 3 clock

period. Since the ACCUM_INT counter is clocked by the

multi-phase clock, the clock rate is either 7 3 clock period

(nominally 40MHz, i.e. 25ns) for Real_lnput mode, or 6 3

clock period (nominally 35MHz, i.e. 28.571429ns) for

Complex_lnput mode. The value stored in the PRESET

toggling the INTERRUPT_PERIOD or

FRONT_END_MODE bits of the SYSTEM_SETUP

Either of these actions will overwrite the previous contents

of the preset value and either one or both methods may

be used. If the Interrupt Counter detects an edge on either

the INTERRUPT_PERIOD or FRONT_END_MODE bits

it will load one of four values in to the PRESET register,

depending upon the new value of both

INTERRUPT_PERIOD and FRONT_END_MODE. These

four presets are as shown in Table 22.

The value for INTERRUPT_PERIOD = low and

FRONT_END_MODE = low is also that loaded on a Master

Reset. Alternatively the ACCUM_INT counter may be

loaded by writing direct to the PROG_ACCUM_INT

location. In this case the new ACCUM_INT period is as

follows:

ACCUM_INT period (Real Input mode)

= (PROG_ACCUM_INT11)37/40MHZ)

ACCUM_INT period (Complex Input mode)

= (PROG_ACCUM_INT 1 1)36/(35MHz)

CHx_SELECT, when set High, enables the Multi-channel

write operations on CHx. This may be used to set several

channels to mostly the same conditions. For a parallel

search for one satellite, operations such as setting each

Carrier DCO to the same frequency; or during that search,

to adjust all selected channels by the same value (such as

a Code Slew to shift the code phases together to a new

search area) could use this feature.

All CHx_SELECT are set low by a (hardware or software)

master reset.

PROG_ACCUM_INT (Write address)

Bits 15 to 13: Not Used.

Bits 12 to 0: ACCUM_INT Division Ratio.

The PROG_ACCUM_INT register location operates in

conjunction with the INTERRUPT_PERIOD bit of the

Table 21

FRONT_END_MODE

(in SYSTEM_SETUP)

Low (Real input mode)

High (Complex input mode)

INTERRUPT_PERIOD

(in SYSTEM_SETUP)

Low

High

Low

High

Preset

(hex)

0B45

1313

0B81

1379

(288511)3(7/40MHz) = 505·0500µs

(488311)3(7/40MHz) = 854·70000µs

(294511)3(6/35MHz) = 505·02857µs

(498511)3(6/35MHz) = 854·74286µs

ACCUM_INT period

Table 22 ACCUM_INT period settings

GP2021

PROG_TIC_HIGH,

PROG_TIC_LOW

(Write Address)

PROG_TIC_HIGH Bits 4 to 0: More significant 5 bits of

the TIC counter division ratio when programmed before a

PROG_TIC_LOW.

PROG_TIC_LOW Bits 15 to 0: Least significant 16 bits

of the TIC counter division ratio.

The PROG_TIC_HIGH and PROG_TIC_LOW register

locations operate in conjunction with the

FRONT_END_MODE bit of the SYSTEM_SETUP register

to set the period of TIC. TIC is generated by a 21-bit binary

down counter when it reaches zero. It then loads to a preset

value stored in its preset register and starts to count down

again. If the preset value is P, the count sequence is P,

P21, P22, ..., 1, 0, P, P21. Hence, the counter divides by

P11, producing an output with a period of (P11) 3 clock

period. Since the TIC counter is clocked by the multi-phase

clock, the clock period is either 7 3 clock period (nominally

25ns at 40MHz) for Real_lnput mode or 6 3 clock period

(nominally 28.571429ns at 35MHz) for Complex_lnput

mode. The value stored in the preset register can be

modified in one of two ways: either by toggling the

FRONT_END_MODE bit of the SYSTEM_SETUP register,

switching into Complex_lnput mode, or by writing to the

PROG_TIC_HIGH/_LOW locations. Either of these actions

will overwrite the previous contents of the preset value. If

the TIC Counter detects an edge on the

FRONT_END_MODE bit it will load one of two values into

the preset register, depending upon its new value. These

two presets are as shown in Table 23.

The value for FRONT_END_MODE = low is also that

loaded on a master reset. Alternatively, the TIC counter

may be loaded by writing directly to the PROG_TIC

locations. This may be achieved in one of two ways: either

the PROG_TIC_HIGH value can be written, followed by

the PROG_TIC_LOW value, (at which point the full 21 bits

are transferred to the preset register), or just the PROG

TiC_LOW value may be written to modify the lower 16 bits

of the preset value. It should be noted that in the former

case, the top 5 bits programmed as PROG_TIC_HIGH

are stored locally to the TIC counter and even if a write to

PROG_TIC_LOW does not directly follow the write to

PROG_TIC_HIGH, the next PROG TIC_LOW write will

still transfer all 21 bits. It is also necessary to ensure that

the write to PROG_TIC_HIGH precedes the write to

PROG_TIC_LOW, rather than follows it. One further point

to note is that the transfer of data to the TIC counter data

latches occurs under control of the multi-phase clock write

cycle and the write to the preset register happens

subsequent to the main internal write. To ensure correct

operation, a write to SYSTEM_SETUP, toggling the

FRONT_END_MODE bit should not be directly preceded

or followed by a write to PROG_TIC_LOW. In addition to

the 300ns delay normally required between write cycles,

a further 100ns delay is required between these two types

of writes. A write to SYSTEM_SETUP toggling the

FRONT_END_MODE bit followed directly by

a PROG TIC_HIGH/PROG_TIC_LOW sequence is

permissible, since the write to PROG_TIC_HIGH does not

instigate a change of the preset register contents within

the TIC counter.

Using the PROG_TIC write locations the TIC period is

asfollows:

TIC period (Real Input mode)

= ((PROG_TIC_HIGH365536)1

PROG_TIC_LOW11)37/40MHZ)

ACCUM_INT period (Complex Input mode)

= ((PROG_TIC_HIGH365536)1

PROG_TIC_LOW11)36/35MHZ)

FRONT_END_MODE

(in SYSTEM_SETUP)

Low (Real input mode)

High (Complex input mode)

Preset loaded

(hex)

08B823

08E6A4

TIC period

(288511)3(7/40MHz) = 505·0500µs

(498511)3(6/35MHz) = 854·74286µs

Table 23 TIC period setting

GP2021

RESET_CONTROL (Write address)

Bit nameBit

Table 24

Not used

CH11_RSTB

CH10_RSTB

CH9_RSTB

CH8_RSTB

CH7_RSTB

CH6_RSTB

CH5_RSTB

CH4_RSTB

CH3_RSTB

CH2_RSTB

CH1_RSTB

CH0_RSTB

MRB, active low software master reset

MRB: When low (a software reset), the effect is similarlr to

a hardware reset except that the clock generator, the time

base generators, measurement data and peripheral

functions are not affected and the Status bits ACCUM_INT,

DISCIP, DISCIP_GLITCH, MEAS_INT, and TIC are not

reset. MRB should be set high to allow access to all of the

various registers. MRB is set high by a hardware reset.

CHx_RSTB: When set active Low, the reset bit inhibits

propagation of the clock phases to the CHx tracking

channel and resets the Accumulated Data flags, Code DCO

and Carrier DCO accumulators, the I and Q accumulators,

and the Code Phase Counter. A CHx_RSTB does not reset

the Carrier Cycle, Code Slew or the Epoch counters. At

the end of the reset, the channel enable resets the code

generator to a previously programmed start phase. This is

all required for the parallel search algorithm of one satellite

signal using many channels in order to start from a known

relative code phase on all the channels. All of the control

registers in CHx can be programmed and read as usual

during the reset state. To restart normal operation in several

different channels at the same time, the corresponding

CHx_RSTB bits should be set high during the same write

operation. All CHx_RSTB are set low by a master reset,

(both hardware and software), so a write low to bit 0 of this

was previously on the bus.

Power consumption can be kept to a minimum by setting

CHx_RSTB Low when a channel is not required.

STATUS (Write Address)

Bits 15 to 0: not used

A write operation to this location, regardless of the data on

the bus, latches the state of all status bits contained in

ACCUM_STATUS_A, ACCUM_STATUS_B, and

ACCUM_STATUS_C registers. Performing a write to

STATUS prior to reading the status registers ensures

reading of stable status values. The latch takes effect within

300ns of the trailing edge of the write pulse. The active

edge transition of the ACCUM_INT signal will also latch

the state of the status bits, thus it is not necessary to write

to STATUS when the status registers are to be read as a

response to the ACCUM_INT signal in an interrupt handling

routine. The write to STATUS is required only when the

status registers are read at times that are not synchronised

to the interrupts. These two mechanisms are mutually

exclusive and should not be used together; if both are used,

a write to STATUS soon after the occurrence of an

ACCUM_INT signal can result in confused readings. To

avoid conflict the INTERRUPT_ENABLE in the

SYSTEM_SETUP register should be set low if writes to

STATUS are to be used.

If the INTERRUPT_ENABLE bit in SYSTEM_SETUP

in the status registers, but a STATUS write access will do

so.

SYSTEM_SETUP (Write address)

Bit name

Bit

Not used

MEAS_INT_SOURCE

OPS-DRIVE-SEL

IPS_3V_MODE

lNTERRUPT_PERIOD

FRONT_END_MODE

INTERRUPT_ENABLE

DISCOP_SELECT_100KHZ

DISCOP_SELECT TIMEMARK

DISCOP_SELECT_CH0_DUMP

DISCOP

CARRIER_MIX_DISABLE

Table 25

MEAS_INT_SOURCE: When set high the MEAS_INT

output is cleared by a read of MEAS_STATUS_A, when

low by a read of ACCUM_STATUS_B. A master reset

forces the MEAS_INT_SOURCE bit low.

OPS_DRIVE_SEL: When set high this control bit increases

the size of the output driver on ACCUM_INT, MEAS_INT,

and D<15:0> pins so as to increase the drive of these pins

if they are driving a large load. Master reset forces

OPS_DRIVE_SEL low.

GP2021

IPS_3V_MODE: When set high this control bit sets the

input buffers on SIGN0, MAG0, SIGN1, and MAG1 for

signals centred on mid-supply, for use with a front end

running from a 3V supply. When low, it sets the thresholds

to TTL levels for 5V operation. Master reset forces IPS_3V

to low.

INTERRUPT_PERIOD: When low, the interrupt period is

set to approximately 505µs and when high it is set to 854s.

For more detail see the description of PROG_ACCUM_INT

on page 38. Master reset forces INTERRUPT_PERIOD

bit to low.

FRONT_END_MODE: Selects either Real_lnput mode

when low or Complex_lnput mode when high. Master reset

forces FRONT_END_MODE to low.

INTERRUPT_ENABLE: When set low the effect of the

ACCUM_INT and MEAS_INT interrupts are disabled

(masked) and when set high both are enabled. Master

reset forces INTERRUPT_ENABLE Low.

Bits 4 to 1: The signal provided on the DlSCOP pin can

be selected according to Table 26.

4321 Signal on DISCOP output

Bit

Table 26 DISCOP selection

CARRIER_MIX_DISABLE: When high the Carrier mixers

are all driven by a fixed ‘11’ level on the Carrier DCO input

port, so that the input data is passed unaltered to the Code

mixer. Master reset forces the CARRIER_MIX_DISABLE

bit low.

TEST_CONTROL (Write address)

0 (Reset condition)

Ch0 DUMP

Timemark

100kHz square wave

Bit name

Bit

Not used

PATH_SEL<2:0>

EN_SCANPATH

Not used

TEST_CACODES

TEST_DATA

TEST_SOURCE

TM_TEST

FE_TEST

EN_DUMMYTICS

EN_DUMMYDUMP

15 to 12

11 to 9

Table 27

The function of the TEST_CONTROL register is purely to

enable various test modes. A master reset (NRESET low)

will set all bits to low, giving normal operation.

EN_DUMMYDUMP: When high, this bit changes the

function of the NOPC/NINTELMOT input pin to be a

DUMMYDUMP input, and if in Standard Interface Mode it

also forces the microprocessor mode to Motorola. A

DUMMYDUMP will operate in the same way as a normal

DUMP (reset all of the code generators and transfer the

contents of all integrators into the Accumulated Data

registers). Each low to high transition of NOPC/

NINTELMOT will cause a DUMMYDUMP and if NOPC/

NINTELMOT is already high when EN_DUMMYDUMP is

set, one will also occur immediately. Selecting Dummy

dump mode does not inhibit normal DUMP events. The

NOPC/NINTELMOT pin must be held high for at least

200 ns for each DUMMYDUMP.

EN_DUMMYTICS: When High this bit changes the function

of the DISCIP input pin to a DUMMYTIC input. This

replaces the TIC from the timebase generator so that a

TIC effect will only occur when there is a low to high

transition on DISCIP, to latch new Measurement Data. The

DISCIP pin must be held high for at least 200ns for each

DUMMYTIC.

FE_TEST: When high this test control forces the SIGN

input to channel 11 and the MAG input to channel 5 both

to low. This allows the evaluation of the front end SIGN

(on channel 5) and MAG (on channel 11 ) duty cycles. The

front end to be tested is selected by the SOURCESEL bits

in CH5_SATCNTL and CH11_SATCNTL. To get the SIGN

and MAG count correctly into the accumulators, both the

carrier and code mixers must be made transparent.

The carrier mixing may be disabled by either (1) Setting

CARRIER_MIX_DISABLE (bit 0 in SYSTEM_SETUP) to

high to force a 11 on the Carrier DCO inputs to all channels

or (2) if continued position finding is required from the other

channels during the test, by setting CH5_ and

CH11_CARRIER_DCO_INCR to all 0s, to give a constant

level (zero frequency). This level should be set to a known

value by putting channels 5 and 11 briefly into the reset

state (by using RESET_CONTROL register bits 6 and 12)

during the time their Carrier DCOs are programmed to

zero frequency. This reset forces the phase to all 0s and

hence the drives to the Prompt in-phase mixer to a fixed

11 and not a randomly selected 22, 21, 11, or 12 that

would result from just setting the frequency.

The C/A code mixing must be disabled by setting

CODE_OFF/ONB (bits 11 in both CH5_ and

CH11_SATCNTL) to High. However, as the period of the

count is set by the DUMPs from the Code Generator, the

DCO clock to the Code Generator must be set to the

GP2021

required frequency by programming the Code DCO even

though the code output is disabled. A typical value is the

frequency for the nominal code chipping rate, so that the

SIGN and MAG counts are over a millisecond.

The results of monitoring the front end of the receiver may

be used for fault diagnosis and also for tuning the

parameters in the software for optimum satellite tracking

with the particular front end or SIGN/MAG duty cycle.

To find the duty cycle of the SIGN signal, channel 5 is

used. The In-phase accumulator CH5_I_PROMPT will add

11 for each SIGN sample at high and will add 21 for each

SIGN sample at low, so if the duty cycle is correct at 50%,

the sum will always be close to zero and only differ by the

imbalance of sampling at the beginning and end of the

integration period.

The duty cycle may be calculated as follows:

N = Total no. of samples in integration period

NSIGN1 = Total no. of samples for which SIGN was high

NSIGN0 = Total no. of samples for which SIGN was low

ACC5 = Total value in the CH5_1_PROMPT accumulator,

as read after a DUMP.

N = NSIGN11NSIGN0

ACC5 = NSIGN12NSIGN0

SIGN duty cycle = R s = NSIGN1/N = (N1ACC5)/2N

(nominally 50%)

To find the duty cycle of the MAG signal, channel 11 is

used. The In-phase accumulator CH11_I_PROMPT will

add 23 for each MAG sample at high and will add 21 for

each MAG sample at low. If the duty cycle is correct (30%),

the sum will be 21·63(Number of samples) plus an

allowance for the imbalance of sampling at the beginning

and end of the integration period. The duty cycle may be

calculated as follows:

N = Total No of samples in integration period

NMAG3 = Total number of samples for which MAG was high

NMAG1 = Total number of samples for which MAG was low

ACC11 = Total value in the CH11_I_PROMPT accumulator,

as read after a DUMP.

N = NMAG31NMAG1

ACC11 = 233(NMAG3)2NMAG1

MAG duty cycle, Rm = NMAG3/N = 2(N1ACC11)/2N

(nominally 30%).

TM_TEST: When High this bit puts all the Tracking Modules

into a test mode, where it is possible to write to all

CHx_CARRIER_CYCLE_COUNTERs and all

CHx_CODE_PHASE_COUNTERs.

TEST_SOURCE: When high this bit enables a self-test

generator formed from the CH0 Code Generator. The data

replaces the SIGN0 and MAG0 inputs. It has a chip rate

and phase set by the CH0_CODE_DCO and a carrier

frequency set by the CH0_CARRIER_DCO. The code is

set by writing the appropriate start value into the

CH0_SATCNTL register, and the CH0_SLEW_COUNTER

can be programmed to delay the start of the code

generation by a number of half code chips.

The three most significant bits of the Carrier DCO are

decoded to give the SIGN with 50% of highs and the MAG

with 25% of highs. The sign of the data pattern is set by

TEST_DATA, EXORed with the CH0 C/A code.

TEST_DATA: This bit sets the sign of the modulation of

the test data generated when TEST_SOURCE is set.

TEST_CACODES: When high, the inverted PROMPT

codes for all channels, 0 to 11, are available for output on

data bus bits 0 to 11 and can be seen in parallel by a read

to any CH6 to CH11 read address.

EN_SCANPATH: When high the chip is in scan test mode,

whereby:

DISCIP 1 becomes SCAN_IN

DISCOP becomes SCAN_OUT

MULTI_FN_IO becomes SCANCLK

NOPC/NINTELMOT becomes SCANSEL

It should be noted that the DISCOP = SCAN_OUT function

may be over-ridden by the DlSCOP_SELECT_100KHZ

function of SYSTEM_SETUP. It should also be noted that

for correct operation the MULTI_FN_IO pin should be

configured as a Discrete or Scan Clock Input via the

IO_CONFIG register.

PATH_SEL<2:0>: To allow for simple factory testing of

the chip, the GP2021 contains six separate scan paths,

one for each of the major counters in the chip. Only one of

these paths may be enabled at any time and the scan

path to be used is selected via the PATH_SEL <2:0> bits

as shown in Table 28.

PATH_SEL

<2:0> Scan path selected

RTC counters

ACCUM_INT counter

TIC counter

100kHz output counter

Timemark pulse width counter

PLL_LOCK filter counter

Not used

000

001

010

011

100

101

11X

Table 28

GP2021

TIMEMARK_CONTROL (Write address)

Bit nameBit

Not used

FREE_RUN_RATIO

FREE_RUN_TIMEMARK

ARM_TIMEMARK

15 to 7

6 to 2

Table 29

The TIMEMARK generator operates in one of two ways,

either in armed mode or in free run mode. (Note that the

term ‘armed’ is not related to ARM). In armed mode setting

the ARM_TIMEMARK bit arms the TIMEMARK generator

which subsequently produces a TIMEMARK output pulse

coincident with the next rising edge of TIC. This then resets

the ARM_TIMEMARK bit ready for a new arming sequence

in the future. Alternatively, the TIMEMARK generator can

be used in free run mode, by setting the

FREE_RUN_TIMEMARK bit high. This disables the

ARM_TIMEMARK bit. In free run mode a TIMEMARK

pulse is produced coincident with the first rising edge of

TIC after the FREE_RUN_TIMEMARK bit has been set,

and then on an integer number of TlCs determined by the

FREE_RUN_RATIO bits. In free run mode the TIMEMARK

period is:

TIMEMARK period = (FREE_RUN_RATIO11 )3TIC

Period (Free run mode)

All the bits of TIMEMARK_CONTROL are cleared to low

by NRESET.

X_DCO_INCR_HIGH1 : (Write Address)

This register may be used to write the high bits for any

Carrier or Code DCO in any channel. A write to

X_DCO_INCR_HIGH must always be followed by a write

to the appropriate CHx_CARRIER_DCO_INCR_LOW or

CHx_CODE_DCO_INCR_LOW to define the destination

and to complete the action.

Using X_DCO_INCR_HIGH rather than CHx_CARRIER

_DCO_I NCR_H IGH gives a quicker way of loading the

whole DCOs values because the _LOW write may follow

the X_DCO_INCR HIGH write immediately (without

incurring a 300ns delay)

Peripheral Functions Registers

The addresses for the Peripheral Functions Registers are

shown in the GP2021 Register Map.

These registers may be either 8 or 16 bits wide. Registers

which are byte wide are accessed via the top 8 bits of the

data bus, D<15:8>. During a byte wide read D<7:0> are

held low.

Each of the registers for the Real Time Clock, Dual UART,

System and General Control functions are described below.

Real Time Clock and Watchdog

The registers in the Real Time Clock are all byte wide.

RTC_LS, RTC_2ND, RTC_MS, (Read Addresses)

The clock time is output in these three eight-bit read only

registers. All three registers are latched when a read is

performed of the LS Byte Register, so this should be read

first. In Power Down mode the clock continues to run but

access to these registers is not possible.

CLOCK RESET (Write Address)

A write to this address resets the clock divider and counter,

regardless of the data word written.

WATCHDOG RESET (Write Address)

A write to this address resets the watchdog timer,

regardless of the data word written.

DUART

All the registers within the DUART are byte wide.

CONFIG_A, CONFIG_B (Write Address)

These registers allow the UARTs to be configured for

receive baud rate, parity and loopback. The configuration

bit functions are shown in Table 30. Other binary

combinations of bit settings (not shown in Table 30) are

invalid and should not be used as the results would be

indeterminate. Note that all bits are set Low by a UARTA/

B or a System reset, thus causing UARTA/B to default to a

receive baud rate of 300, no parity and no loopback.

11 10 9 8 Receiver Baud rate

300

600

1200

2400

4800

9600

19.2k

38.4k

76.8k

Parity

No parity: bit not set or checked for

Odd parity: parity added so that the

total number of ‘1’s in the word is even

Even parity: parity added so that the

total number of ‘1’s in the word is even

Loopback

No loopback: normal operation

Loopback: the Tx output drives the Rx

input and Tx pin is held HIGH

Test mode

Test mode bit in ChA used for chip

testing only. This bit must be set Low

for Normal operation

Test mode

FunctionBit setting

Table 30 Configuration of UARTs

GP2021

STATUS_A, STATUS_B (Read Address)

Reading from these register addresses will give the current

value of the channels status bits. The Status bit functions

are as shown in Table 31. When reset, all bits are low.

RX valid data available

RX FIFO full

RX FIFO overflow

TX transmitting

TX FIFO full

Parity error occurred

Framing error

Not used (held high)

No RX data

RX FIFO not full

Read of UART

status register

TX register empty

TX FIFO not full

Read of UART

status register

Read of UART

status

Bit Set (high) by Clear (low) by

Table 31 Status bits available when reading the

STATUS_A and STATUS_B registers

RESET_A,

RESET_B

(Write Address)

Writing to this register will reset the UART A/B, regardless

of the data word written.

TX_DATA_A,

TX_DATA_B,

RX_DATA_A,

RX_DATA_B

(Write / Read Address)

These are Read/Write addresses to UARTs A and B, which

allow bytes to be written to the TX FlFOs or received from

the RX FlFOs.

TX_RATE_A,

TX_RATE_B

(Write Address)

These are write registers for UARTs A and B, which allow

the Transmit baud rates to be set as shown in Table 32.

Other binary combinations of bit settings (not shown in

Table 32) are invalid and should not be used as the results

would be indeterminate.

Bits 12 to 15 are not used and may be set high or low.

Note that bits 8 to 11 are set low by a UART A/B or System

reset, thus causing the Transmitter to default to a Baud

rate of 300.

SYSTEM CONTROL

WAIT_STATE

(Write/Read address)

This is a Read/Write register (8 bits wide), which allows

the ROM (Read/Write) wait state and EEPROM and Spare

(Read) wait states to be configured via bits 8 to 11.

EEPROM and Spare read accesses consist of 2 to 5 wait

states whilst MCLK is high, increasing the read access

time, followed by 1 trailing wait state whilst MCLK is low to

allow for a greater bus release time. The Chip revision

number appears on bits 12 to 15 when read.

Bit 9

Bit 10

Bit 8

Bit 11

ROM (Read/Write) Wait states

3 (note1)

Unused (3)

EEPROM and Spare (Read) Wait states

211

311

411

511 (note 1)

Bit setting Transmit Baud rate

300

600

1200

2400

4800

9600

19·2k

38·4k

76·8k

Table 32 Transmit Baud rate settings in the TX_RATE_A

and TX_RATE_B registers

Note 1. The conditions after a reset are ROM Wait states = 3,

EEPROM and Spare Wait states = 511

SYSTEM_CONFIG

(Write/Read Address)

This is a Read/Write register (8 bits wide), which allows

the Watchdog Function to be enabled and disabled via

bit 9. Note that following a system reset this bit is set low,

thus enabling the watchdog.

Table 33 WAIT_STATE register settings

Bit 9 Watchdog function

Enabled

Disabled

Table 34 Enabling the Watchdog function through the

SYSTEM_CONFIG register

Bits 5 to 10 and 13 are not used and could be set high or

low. The Chip revision number appears on bits 12 to 15

when read.

SYSTEM_ERROR_STATUS

This is an 8-bit wide read only register, and allows the

source of a system reset to be determined via bits 11 to 8.

All bits are reset low after being read. The Chip revision

number appears on bits 12 to 15 when read.

GP2021

Bit 8: Set during a system reset, when the source of the

reset is a PLL_LOCK failure.

Bit 9: Set during a system reset, when the source of the

reset is the Watchdog.

Bit 10: Set during a system reset, when the source of the

reset is a POWER_GOOD failure.

Bit 11: Set during a system reset, when the source of the

reset is the external NRESET_IP. Note that

this reset source is only available in Standard

Interface mode.

CHIP_REVISION

(Read Addresses)

The CHIP_REVISION register is a read only register

which exists as the high 4 data bits of the Wait state, System

Configuration and System Error Status registers. A read

of any of these three registers will output the

CHIP_REVISION information on bits 15 to 12. This register

is intended to allow software discrimination of revisions of

the GP2021, both pre-production revisions and possible

customer-specific variants. The initial production version

of the GP2021 will have a CHIP_REVISION of 0011.

DATA_RETENT

(Write/Read Address)

This is a byte wide Read/Write register which can be used

to store a predetermined value, which can be interrogated

in order to determine whether a total power loss (below

the data retention level ) has occurred.

GENERAL CONTROL

IO_CONFIG

(Write/Read Address)

The IO_CONFIG register is a full 16-bit wide read/write

read location which allows the controlling microprocessor

to view the input level on all the Discrete and Multi Function

inputs, and a 16-bit wide write location for configuration of

the Discrete and Multi Function l/O pins.

IO_CONFIG Read: A read of the IO_CONFIG address

will latch the logic level of a number of input pins and output

these levels to the microprocessor via the 16-bit data bus.

This allows the microprocessor to read the input levels on

all the discrete and multi-function Inputs from a single

location. The bit allocations are as sown in Table 35.

It should be noted that the usefulness of a number of these

inputs as discrete Inputs for System Control is dependent

upon the Interface Mode of the GP2021. For instance, it is

possible to use the NOPC/NINTELMOT pin as a discrete

input in ARM System mode if the DEBUG function is

disabled, whereas this pin could not be used as a discrete

input in Standard Interface mode. Similarly, NMREQ could

be used as a discrete input in Standard Interface mode

but not in ARM System mode.

Input pinBit

Table 35

RXB

RXA

DISCOP

DISCIP

MAG1

SIGN1

MAG0

SIGN0

MULTI_FN_IO

NBRAM

DISCIO

NARMSYS

NBW/WRPROG

NMREQ

NOPC/NINTELMOT

NRW

IO_CONFIG Write: The IO_CONFIG write location allows

the configuration of the multi-purpose I/O pins DISCIO and

MULTI_FN_IO. The register bit assignments are as shown

in Table 36

DISCIO_CONFIG: When set high this bit configures the

DISCIO pin as a discrete output, when low the DISCIO

pin is configured as a discrete input. NRESET low sets

the DISCIO_CONFIG bit low.

DISCIO_SELECT TIMEMARK,

DISCIO_SELECT_100KHZ,

DISCIO_LEVEL

When configured as an output, the DISCIO pin can be set

up to give a signal as determined by Table 37.

At power on reset, the DISCIO output value = 0 setting is

chosen. The 100kHz square wave is derived from the

Master Clock and is useful for measuring its drift.

Bit nameBit

15 to 13

9 to 8

7 to 4

Not Used

MULTI_FN_IO_SELECT_TIMEMARK

MULTI_FN_IO_SELECT_1 00KHZ

MULTI_FN_IO_LEVEL

MULTI_FN_IO_CONFIG

Not Used

DISCIO_SELECT_TIMEMARK

DISCIO_SELECT_1 00KHZ

DISCIO_LEVEL

DISCIO_CONFIG

Table 36

GP2021

DISCIO output value

Bit

321

100kHz square wave

TIMEMARK

Table 37 DISCIO selection

MULTI_FN_IO_SELECT TIMEMARK,

MULTI_FN_IO_SELECT_100KHz,

MULTI_FN_IO_LEVEL:

When configured as an output, the MULTI_FN_IO pin can

be setup to give a signal as shown in Table 38.

MULTI_FN_IO output value

Bit

12 11 10

100kHz square wave

TIMEMARK

Table 38 MULTI_FN_IO selection

MULTI_FN_IO_CONFIG: These 2 bits configure the

function of the MULTI_FN_IO input as shown in Table 39.

MULTI_FN_IO_CONFIG functionBits <9:8>

Digital system Test Enable signal

TRIGGER input

Discrete input (see description)

Discrete output

Table 39

NRESET low sets bits 9 and 8 to Low.

MULTI_FN_IO as Digital System Test Enable Input:

Allows testing of the digital section of the system board. In

this mode, when MULTI_FN_IO is high, the RXA pin

replaces the differential master clock Inputs and the RXB

pin acts as an RTC Reset input. The PLL_LOCK filter is

also disabled. For more information see the digital system

Test mode description.

MULTI_FN_IO as TRIGGER Input: The DEBUG function

is enabled if in ARM System mode and the MULTI_FN_IO

pin acts as the TRIGGER input to the DEBUG block. For

more information see the DEBUG Block Description.

MULTI_FN_IO as Discrete Input/Scan Clocks: In this

mode the pin has two functions: As a discrete input and as

the Scan Clocks input for chip scan path testing. It should

be noted that the MULTI_FN_IO pin should only be used

as a discrete input with caution. Since the Master Reset

default is for MULTI_FN_IO to act as the Digital System

Test Enable input it must be guaranteed that anything

driving this pin as a discrete input must have a low output

until the IO_CONFIG register can be written to and Discrete

Input Mode enabled.

RTC_TEST_COUNT: When set high this bit splits up the

24-bit counter of the RTC which counts seconds into a

number of 4-bit counters to allow easier chip testing. The

24-bit RTC Counter is not Scan Path testable. A Master

Reset sets the RTC_TEST_COUNT bit low.

RTC_RESET_ENABLE: When set high this bit enables

the RXB pin to act as an RTC reset input, which then resets

the RTC and Watchdog counters whenever RXB is taken

high. This function is intended for factory testing of the

GP2021. NRESET low forces the RTC_RESET_ENABLE

bit low.

WDOG_RESET_DISABLE: When set high this bit inhibits

the production of System resets from the Watchdog

counter, without disabling the Watchdog counter itself. This

function is intended for Scan Path Testing of the Watchdog

and RTC Counters. NRESET low forces the

WDOG_RESET_DISABLE bit low.

DATA_BUS_TEST

(Write / Read Address)

This is a 16-bit read/write register, whose function is to

allow a simple test of the 16- bit wide data bus to be

performed, by writing a 16-bit number and by checking

that the same value can be read back.

TEST_CONFIG

(Write Address)

The TEST_CONFIG register is a 3-bit wide write only

of the Correlator but contains chip test control bits for

Peripheral Functions. The register bit assignments are

shown in Table 40.

Bit nameBit

RTC_TEST_COUNT

RTC_RESET ENABLE

WDOG_RESET_DISABLE

Table 40

GP2021

ELECTRICAL CHARACTERISTICS

TAMB = 240°C to 185°C, VDD = 5V 610%. The input thresholds and output voltage limits for the logic signal pins are

tested and guaranteed by production test. All other parameters are guaranteed by characterisation and design. They

apply within the specified ambient temperature and supply voltage ranges unless otherwise stated.

Characteristic Conditions

Max.

Min.

Value

Units

Typ.

Symbol

Supply current

No channels enabled.

4 channels enabled.

8 channels enabled.

12 channels enabled.

Power Down mode

Battery backup voltage

All TTL inputs, with and without

pull-up or pull-down resistors

High level input voltage

Low level input voltage

Schmitt trigger inputs Type ST1

Positive-going threshold

Negative-going threshold

Hysteresis

Schmitt trigger inputs Type ST2

Positive-going threshold

Negative-going threshold

Hysteresis

Master clocks CLK_T and CLK_I

Input voltage high

Input voltage low

Differential sinewave

Differential sinewave mid-point

Single sinewave

Crystal oscillator type XTLI, XTLO

Frequency range

Amplifier transconductance

Output impedance

Crystal specification

Frequency

Series resistance

Load capacitance

IDD

VBATT

VT1

VT2

VT1

VT2

VIH

VIL

fOSC

2·2

2·0

0·8

0·35

0·72

0·3

0·8V

130

600

220

1·9

1·2

0·7

1·72

1·10

0·62

4·3

550

32·768

150

500

2·3

2·32

0·2VDD

1000

2500

100

µA

mVp-p

kHz

µA/V

kΩ

kHz

kΩ

VDD = 2·2V to 3·3V (note 1)

VDD = 5·0V (note1)

Power Down mode

VDD = 3V

Note 2

DC coupled

AC coupled

GP2021

Electrical Characteristics (continued)

Characteristic Conditions

Max.Min.

Value

Units

Typ.

Symbol

VOH

VOL

IOS

IOZ

COUT

VOH

VOL

IOS

IOZ

COUT

VOH

VOL

IOS

IOZ

COUT

VOH

VOL

IOS

IOZ

COUT

0·8VDD

270

150

,10

135

,10

0·4

µA

IOH = 212mA

IOH = 12mA

VDD = max, VO = VDD

VDD = max, VO = 0V

VOH = GND or VDD

IOH = 26mA

IOH = 6mA

VDD = max, VO = VDD

VDD = max, VO = 0V

VOH = GND or VDD

IOH = 24mA

IOH = 4mA

VDD = max, VO = VDD

VDD = max, VO = 0V

VOH = GND or VDD

IOH = 22mA

IOH = 2mA

VDD = max, VO = VDD

VDD = max, VO = 0V

VOH = GND or VDD

Output types OP6 and OPT6

Output voltage high

Output voltage low

Output short circuit current

Tri-state output leakage current

Output capacitance

Output types OP3 and OPT3

Output voltage high

Output voltage low

Output short circuit current

Tri-state output leakage current

Output capacitance

Output types OP2 and OPT2

Output voltage high

Output voltage low

Output short circuit current

Tri-state output leakage current

Output capacitance

Output types OP1 and OPT1

Output voltage high

Output voltage low

Output short circuit current

Tri-state output leakage current

Output capacitance

NOTES

1. These values apply when the 32kHz oscillator circuit is not running.

2. The input pair CLK_T, CLK_I may be driven by CMOS logic levels (DC coupled) or A. coupled or by a low amplitude differential

sinewave (DC coupled e.g. GP2010). If a single logic level is to be used this should drive CLK_T with the CLK_I pin biased to mid

supply. If a single sinewave clock is to be used this should drive CLK_T through a capacitor, with both of the CLK_T/CLK_I pins

biased to approximately two thirds supply. See Figure 24 for a suggested circuit.

3. Any unused inputs must be tied high or low.

4. The operation of the feature whereby input levels and output drive strengths can be modified is not guaranteed by the existing

factory testing procedure.

VDD

VSS

100k100k

180k

0·1-1nF

CLK_T

CLK_I

0·1-1nF

600mV

SINEWAVE

CLK_T

CLK_I

VDD

VSS

100k

CMOS CLK_T

CLK_I

OPCLK1

OPCLK2

GP2010

DIFFERENTIAL

OUTPUT

(a) Single ended CMOS (b) Single 600mV sinewave (c) Differential

Figure 24 Clock interconnect options

GP2021

Pin no.

cont…Table 41

MULTI_FN_IO

POWER_GOOD

NRESET_OP

NARMSYS

XIN

XOUT

TXA

TXB

RXA

RXB

NROM/NC

NEEPROM/NC

NSPARE_CS/NC

VDD

VSS

NRAM/NC

NW0/NCOP .

NW1/NCOP

NW2/NCOP

NW3/NCOP

NRD/NCOP

ARM_ALE / NC

DBE/NC

ACCUM_INT

MEAS_INTOP

NBW/WRPROG

NMREQ/DISCIP2

NOPC/NINTELMOT

NRW/DISCIP3

MCLK/NC

ABORT/MICRO_CLK

DISCIO l/O

A22/READ

VDD

VSS

A21/NCS

A20/WREN

A1/ALE_IP

A0/NRESET_IP

Pin name

I/O

ST2

VDD

VSS

ST2

VDD

VSS

TTL/ST2

I/O

ST2

None

XTLI

ST2

TTL

None

TTL/ST2

None

TTL/ST2

TTL

TTL/ST2

TTL

Pull Up/Dn

75kΩ dn

None

Pin type Input type Output type Tristate

OPT3

OP3

XTLO

OP6

OPT6

OP6

OPT1/OPT2

OP6

OP3

OPT3

OPT3/OPT/6

YES

Notes

Xtal In

Xtal Out

2,6

2,7

Pin Types

Table 41 defines the type of each GP2021 pin and refers to additional notes relating to them.

GP2021

Pin no. Pin name Pull Up/DnPin type Input type Output type Tristate Notes

Table 41 (continued)

VDD

VSS

D10

D11

D12

D13

D14

D15

PLL_LOCK

VDD

DISCOP

VSS

CLK_T

CLK_I

VSS

SAMPCLK

VDD

NBRAM / DISCIP4

SIGN0

MAG0

SIGN1

MAG 1

DISCIP1

I/O

VDD

VSS

I/O

VDD

VSS

VDD

TTL

ST2

Diff

ST2

ST2/ST 1

ST2/ST1

ST2

None

OPT3/OPT6

OPT3

OP2

YES

4,12

5,13

NOTES

1. Although MULTI_FN_IO is capable of being used as a discrete input, this is not advised since if this pin is driven high at power up,

Digital Test Mode will be selected and correct operation will not ensue.

2. Output has power level 1 when OPS_DRIVE_SEL is low in the SYSTEM_SETUP register. Output has power level 2 when

OPS_DRIVE_SEL is high in the SYSTEM_SETUP Register.

3. Input has TTL thresholds in ARM System mode, but has Schmitt trigger (type ST2) thresholds in Standard Interface mode.

4. Output has power level 3 when OPS_DRIVE_SEL is low in the SYSTEM_SETUP Register. Output has power level 6 when

OPS_DRIVE_SEL is high in the SYSTEM_SETUP register.

5. Input has Schmitt trigger type ST2 thresholds when IPS_3V_MODE is low in the SYSTEM_SETUP register. When high they

have ST1 thresholds.

6. Usually connected to NFIQ of the ARM60 processor.

7. Usually connected to NIRQ of the ARM60 processor.

8. Characterisation data for this pin is with CL = 10pF.

9. Characterisation data for this pin is with CL = 20pF.

10. Characterisation data for this pin is with CL = 30pF

11. Characterisation data for this pin is with CL = 50pF.

12. Characterisation data for this pin is with CL = 55pF.

13. Setup and Hold times for the GPS data applied on pins SIGN0, MAG0, SIGN1 and MAG1 are with respect to the rising edge of

SAMPCLK. Setup time = 15ns, Hold time = 1 ns (i.e. data should not change during the period between 15ns and1ns before the

rising edge of SAMPCLK; where SAMPCLK is assumed to be unloaded. The SAMPCLK signal will tend to be further delayed by

about 0·1 ns/pF of load capacitance).

GP2021

TIMING CHARACTERISTICS

VALID

MCLK

VALID

tMCHALL

tMCHDBH

tMCLALH

tMCLDBL

ARM INTERNAL ADDRESS

ARM_ALE

A<22:20>, A<9:0>

DBE

D<15:0>

Timing parameter Symbol

tMCLALH

tMCHALL

tMALDLBL

tMCHDBH

Min.

20·5

0·5

Max.

0·5

1·5

Units

Figure 25 ARM60 interface timings

MCLK Low to ALE High

MCLK High to ALE Low

MCLK Low to DBE Low

MCLK High to DBE High

MCLK

NRAM

A<22:20>

DBE

D<15:0> ARM DATA

tADVNRAL

tNWL

tNRALNWH

tMCLNWH

tDBHNWH

VALID

Timing parameter Symbol Min.

0·5

Max.

24·5

Units

NRAM Low to NW0-3 High

MCLK Low to NW0-3 High

DBE High to NW0-3 High

NW0-3 Low

tNRALNWH

tMCLNWH

tDBHNWH

tNWL

tADVNRAL

Figure 26 ARM mode RAM Write timings

GP2021

Timing parameter Symbol Min.

16·5

15·5

2·5

Max.

22·5

11·5

Units

Figure 27 ARM mode RAM Read timings

NRAM Low to MCLK Low

NRD Low to MCLK Low

NRD High to DBE High

MCLK Low to NRD High

Address Valid to NRAM Low

tNRALMCL

tNRDLMCL

tNRDHDBH

tMCLNRDH

tADVNRAL

MCLK

NROM

A<22:20>, A<9:0>

DBE

D<15:0> ARM DATA

tADVNROL

tNWL

VALID

tDBHNWH

tNROLNWL

tNWHMCL

tNROL

tNWHNROH

tNWH

Timing parameter

NROM Low

NROM Low to NW0-3 Low

DBE High to NW0-3 High

NW0-3 Low

NW0-3 High to MCLK Low

NW0-3 High to NROM High

NW0-3 High

Address Valid to NROM Low

Symbol Min.

100

27·5

Max.

21·5

7·5

Units

Notes

tNROL

tNROLNWL

tDBHNWH

tNWL

tNWHMCL

tNWHNROH

tNWH

tADVNROL

Note 1. 150ns/extra wait state

Figure 28 ARM mode ROM (Flash) Write timings

MCLK

NRAM

A<22:20>

DBE

D<15:0> RAM DATA

tADVNRAL

tNRDLMCL

tNRALMCL

NRD

VALID

tMCLNRDH

tNRDHDBH

GP2021

MCLK

NROM

A<22:20>, A<9:0>

DBE

D<15:0> ROM DATA

tADVNROL

tNRDLMCL

NRD

VALID

tNROLMCL

tMCLNRDH

tNRDHDBH

Timing parameter Symbol Min.

2·5

Max.

74·5

Units

Notes

tNROLMCL

tNRDLMCL

tNRDHDBH

tMCLNRDH

tADVNROL

NROM Low to MCLK Low

NRD Low to MCLK Low

NRD High to DBE High

MCLK Low to NRD High

Address Valid to NROM Low

Note 1. 150ns/extra wait state

Figure 29 ARM mode ROM Read timings

MCLK

NEEPROM/NSPARE_CS

A<22:20>, A<9:0>

DBE

D<15:0> ARM DATA

tADVNEEL

tNWL

VALID

tDBHNWH

tNEELNWL

tNWHDBL

tNEEL

tNWH

Timing parameter Symbol Min.

348

200

150

168

2·5

Max.

Units

NEEPROM Low

NEEPROM Low to NW0-3

NW0-3 Low

NW0-3 High

DBE High to NW0-3 High

NW0-3 High to DBE Low

tNEEL

tNEELNWL

tNWL

tNWH

tDBHNWH

tNWHDBL

tADVNEEL

Figure 30 ARM mode EEPROM Write timings

GP2021

MCLK

NEEPROM/NSPARE_CS

A<22:20>, A<9:0>

DBE

D<15:0> EEPROM/SPARE DATA

tADVNEEL

tNRDLMCL

NRD

VALID

tNEELMCL

tMCLNRDH

tNRDHDBH

Timing parameter Min.

124·5

117

2·5

Max.

Units

Notes

Note 1. 150ns/extra wait state

NEEPROM Low to MCLK Low

NRD Low to MCLK Low

NRD High to DBE High

MCLK Low to NRD High

Address Valid to NEEPROM Low

Symbol

tNEELMCL

tNRDLMCL

tNRDHDBH

tMCLNRDH

tADVNEEL

Figure 31 ARM mode EEPROM Read timings

WREN

ALE_IP

A<9:2>

NCS

D<15:0>

READ (HIGH)

tWCLWCH

tALLWCH

tALHWCL tWCHALH

tALHALL

VALID

tADVALL

tALLADI

tDAVWCH

tWCHDAI

Timing parameter Notes

Units

Max.Min.

Symbol

ALE_IP High to WREN and NCS Low setup time

ALE_IP High to ALE_IP Low pulse width

ALE_IP Low to WREN or NCS High pulse width

WREN and NCS Low to WREN or NCS High pulse width

WREN or NCS High to ALE_IP High hold-off time

Address Valid to ALE_IP Low setup time

ALE_IP Low to Address Invalid hold time

Data Valid to WREN or NCS High setup time

WREN or NCS High to Data Invalid hold time

tALHWCL

tALHALL

tALLWCH

tWCLWCH

tWCHALH

tADVALL

tALLADI

tDAVWCH

tWCHDAI

Note 1. Write inhibited until ALE_IP falling edge

Figure 32 Intel 486 mode Write (NINTELMOT = 0, WPROG = 1)

GP2021

READ

ALE_IP

A<9:2>

NCS

D<15:0>

WREN (HIGH)

tALHRCL tRCHALH

tALHALL

ADDR VALID

DATA VALID

tADVALL tALLADI

tALLDAV tRCHDAZ

Timing parameter Notes

1,2,3

Units

Max.Min.

Symbol

tALHRCL

tALHALL

tRCHALH

tADVALL

tALLADI

tRCLDAV

tRCHDAZ

ALE_IP High to READ and NCS Low setup time

ALE_IP High to ALE_IP Low pulse width

READ or NCS High to ALE_IP High hold time

Address Valid to ALE_IP Low setup time

ALE_IP Low to Address Invalid hold time

ALE_IP Low to Data Valid propagation delay

READ or NCS High to Data High Impedance

NOTES

1. READ inhibited until ALE_IP falling edge.

2. The ALE_IP Low to Data Output Valid Delay assumes ALE_IP is overlapping the READ and NCS Low time. If not, the

tALLDAV parameter applies from the point at which both READ and NCS are Low.

3. The Data Out propagation delay is for a data bus load of 50pF.

Figure 33 Intel 486 mode Read (NARMSYS = 1, NINTELMOT = 0, WPROG = 1)

WREN

ALE_IP (HIGH)

A<9:2>

NCS

D<15:0>

READ (HIGH)

tWCLWCH

tADVWCL tWCHADI

VALID

tDAVWCH

tWCHDAI

Timing parameter NotesUnits

Max.Min.

Symbol

WREN and NCS Low to WREN or NCS High pulse width

Address Valid to WREN and NCS Low setup time

WREN or NCS High to Address Invalid Hold time

Data Valid to WREN or NCS High setup time

WREN or NCS High to Data Invalid hold time

tWCLWCH

tADVWCL

tWRHADI

tDAVWCH

tWCHDAI

Figure 34 Intel 186 mode Write with ALE_IP tied high (NARMSYS = 1, NINTELMOT = 0, WPROG = 0)

GP2021

READ

ALE_IP (HIGH)

A<9:2>

NCS

D<15:0>

WREN (HIGH)

tADLRCL tRCHADI

ADDRESS VALID

tRCLDAV tRCHDAZ

DATA VALID

Timing parameter Notes

Units

Max.Min.Symbol

Address Valid to READ and NCS Low setup time

READ or NCS High to Address Invalid hold time

READ and NCS Low to Data Valid propagation delay

tADVRCL

tRCHADI

tRCLDAV

tRCHDAZ

423

Note 1. The Data Out propagation delay is for a Data Bus load of 50pF.

Figure 35 Intel 186 mode Read with ALE_IP tied high (NARMSYS = 1, NINTELMOT = 0, WPROG = 0)

Timing parameter NotesUnits

Max.Min.

Symbol

ALE_IP High to WREN and NCS Low setup time

ALE_IP High to ALE_IP Low pulse width

WREN and NCS Low to WREN or NCS High pulse width

WREN or NCS High to ALE_IP High hold time

Address Valid to WREN and NCS Low setup time

Address Valid to ALE_IP Low setup time

ALE_IP Low to Address Invalid hold time

Data Valid to WREN or NCS High setup time

WREN or NCS High to Data Invalid hold time

tALHWCL

tALHALL

tWCLWCH

tWCHALH

tADVWCL

tADVALL

tALLADI

tDAVWCH

tWCHDAI

Figure 36 Intel 186 mode Write with ALE_IP being pulsed (NARMSYS = 1, NINTELMOT = 0, WPROG = 0)

WREN

ALE_IP

A<9:2>

NCS

D<15:0>

READ (HIGH)

tWCLWCH

tALHWCL tWCHALH

tALHALL

VALID

tADVALL

tALLADI

tDAVWCH

tWCHDAI

tADVWCL

GP2021

Timing parameter Notes

Units

Max.Min.

Symbol

ALE_IP High to READ and NCS Low setup time

ALE_IP High to ALE_IP Low pulse width

READ or NCS High to ALE_IP High hold off time

Address Valid to READ and NCS Low setup time

Address Valid to ALE_IP Low setup time

ALE_IP Low to Address Invalid hold time

READ and NCS Low to Data Valid propagation delay

READ or NCS High to Data High Impedance

tALHRCL

tALHALL

tRCHALH

tADVRCL

tADVALL

tALLADI

tRCLDAV

tRCHDAZ

Note 1. The Data Out propagation delay is for a Data Bus load of 50pF.

READ

ALE_IP

A<9:2>

NCS

D<15:0>

WREN (HIGH)

ALHRCL

RCHALH

ALHALL

ADDR VALID

DATA VALID

ADVALL

ALLADI

RCLDAV

RCHDAZ

Figure 37 Intel 186 mode Read with ALE_IP being pulsed (NARMSYS = 1, NINTELMOT = 0, WPROG = 0)

GP2021

Figure 38 Motorola mode Write, ALE_IP non-overlapping WREN and NCS (NARMSYS = 1, NINTELMOT = 1, WPROG = X)

Timing parameter NotesUnits

Max.Min.

Symbol

WREN or NCS Inactive to WREN and NCS active

WREN and NCS active to WREN or NCS inactive

ALE_IP High to ALE_IP Low pulse width

WREN or NCS Inactive to ALE_IP Low Hold off time

Address Valid to ALE_IP Low setup time

ALE_IP Low to Address Invalid hold time

READ Valid to WREN and NCS Active setup time

WREN and NCS Active to READ Invalid hold time

DATA Valid to WREN or NCS Inactive setup time

WREN or NCS Inactive to DATA Invalid hold time

tWCIWCA

tWCAWCI

tALHALL

tWCIALL

tADVALL

tALLADI

tRDVWCA

tWCARDI

tDAVWCI

tWCIDAI

1,2

NOTES

1. WREN is active high, NCS is Active low.

2. READ is transparently latched by WREN and NCS being active.

3. There is no parameter specified for WREN or NCS Inactive to ALE_IP High, since the internal ALE signal is disabled

until after the end of the internal Read or Write Strobe; hence the need for the tWCIALL parameter.

WREN

ALE_IP

A<9:2>

NCS

D<15:0>

READ

tWCIWCA

tDAVWCI

VALID

tWCAWCI

tWCARDI

tRDVWCA

tWCIALL

tALHALL

tADVALL tALLADI

tWCIDAI

GP2021

Timing parameter NotesUnits

Max.Min.Symbol

NOTES

1. WREN is active high, NCS is active low.

2. READ is transparently latched by WREN and NCS being active.

3. There is no parameter specified for WREN or NCS Inactive to ALE_IP High, since the internal ALE signal is disabled

until after the end of the internal Read or Write Strobe; hence the need for the tWCIALL parameter.

WREN or NCS Inactive to WREN and NCS active

ALE_IP High to ALE_IP Low pulse width

WREN or NCS Inactive to ALE_IP Low Hold time

Address Valid to ALE_IP Low setup time

ALE_IP Low to Address Invalid Hold time

READ Valid to WREN and NCS Active setup time

WREN and NCS Active to READ Invalid Hold time

WREN or NCS Active to DATA valid

WREN or NCS Inactive to DATA High impedance

tWCIWCA

tALHALL

tWCILALL

tADVALL

tALLADI

tRDVWCA

tWCARDI

tWCADAV

tWCIDAZ

1,2

WREN

ALE_IP

A<9:2>

NCS

D<15:0>

READ

tWCIWCA

tWCADAV

VALID

tRDIWCA

tRDVWCA

tWCIALL

tALHALL

tADVALL tALLADI

tWCIDAZ

Figure 39 Motorola mode Read, ALE_IP non-overlapping WREN and NCS (NARMSYS = 1, NINTELMOT = 1, WPROG = X)

GP2021

WREN

ALE_IP

A<9:2>

NCS

D<15:0>

READ

tWCIWCA

tDAVWCI

VALID

tWCAWCI

tWCARDI

tRDVWCA

tWCIALL

tALHWCA

tWCAADI

tWCIDAI

tWCAALL

tADVWCA

Timing parameter Notes

Units

Max.Min.

Symbol

WREN or NCS Inactive to WREN and NCS Active

WREN and NCS Active to WREN or NCS Inactive

ALE_IP High to WREN or NCS Active pulse width

WREN and NCS Active to ALE_IP Low hold time

Address Valid to WREN and NCS Active setup time

WREN and NCS Active to Address Invalid hold time

READ Valid to WREN and NCS Active setup time

WREN and NCS Active to DATA Invalid hold time

DATA Valid to WREN or NCS Inactive setup time

WREN or NCS Inactive to DATA Invalid hold time

tWCIWCA

tWCAWCI

tALHWCA

tWCAALL

tADVWCA

tWCAADI

tRDVWCA

tWCADAI

tDAVWCI

tWCIDAI

1,2

1,3

NOTES

1.WREN is active high, NCS is active low.

2.If ALE_IP does not overlap WREN and NCS active by tWCALL then the timings for ALE_IP both overlapping and non-

overlapping WREN and NCS active must be met.

3.READ is transparently latched by WREN and NCS being active.

4.There is no parameter specified for WREN or NCS Inactive to ALE_IP High, since the internal ALE signal is disabled

until after the end of the internal Read or Write Strobe; hence the need for the tWCIALL parameter.

Figure 40 Motorola mode Read, ALE_IP overlapping WREN and NCS (NARMSYS = 1, NINTELMOT = 1, WPROG = X)

GP2021

WREN

ALE_IP

A<9:2>

NCS

D<15:0>

READ

tWCIWCA

tWCADAV

ADDR VALID

DATA VALID

tWCAALL

tRDVWCA

tALHWCA

tADVWCA

tWCIDAZ

tWCAADI

tWCAWCI

tRDIWCA

Timing parameter NotesUnits

Max.Min.

Symbol

WREN or NCS Inactive to WREN and NCS active

WREN and NCS active to WREN or NCS inactive

ALE_IP High to WREN and NCS Active pulse width

WREN and NCS Active to ALE_IP Low hold time

Address Valid to WREN and NCS Active setup time

WREN and NCS Active to Address Invalid hold time

READ Valid to WREN and NCS Active setup time

WREN and NCS Active to READ Invalid hold time

DATA Valid to WREN or NCS Inactive setup time

WREN or NCS Inactive to DATA Invalid hold time

tWCIWCA

tWCAWCI

tALHWCA

tWCAALL

tADVWCA

tWCAADI

tRDVWCA

tWCARDI

tDAVWCI

tWCIDAI

1,2

1,3

NOTES

1. WREN is active High, NCS is Active Low.

2. If ALE_IP does not overlap WREN and NCS active by tWCAALL then the timings for ALE_IP both overlapping

and non-overlapping WREN and NCS active must be met.

3. READ is transparently latched by WREN and NCS being active.

4. There is no parameter specified for WREN or NCS Inactive to ALE_IP High, since the internal ALE signal is disabled

until after the end of the internal Read or Write Strobe; hence the need for the tWCIALL parameter.

Figure 41 Motorola mode Read, ALE_IP overlapping WREN and NCS (NARMSYS = 1, NINTELMOT = 1, WPROG = X)

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