TC358762XBG CMOS Digital Integrated Circuit Silicon Monolithic TC358762XBG Mobile Peripheral Devices Overview TC358762XBG TC358762XBG chip de-serializes the stream into a parallel one. The parallel output bus can be either a DPI or a DBI bus. The usage of either DPI or DBI bus is mutually exclusive. The DSI host controls/configures TC358762XBG chip via DSI's P-VFBGA64-0505-0.50BZ Generic Long Write packets. The host controls (commands) the Weight: 41 mg (Typ.) peripheral display device by sending DSI packets to TC358762XBG. TC358762XBG routes the commands either through DBI host, SPI master or DBI-C host interface, I/F, block to the peripheral device. TC358762XBG supports both DCS and generic commands. The commands output through these interfaces are intended for the peripheral display device to interpret and execute; TC358762XBG does not interpret them, except a few DCS commands mentioned explicitly in this document. TC358762XBG supports bi-directional DSI link. The host reads TC358762XBG's registers via DSI's Generic Read (2 parameter) packets. Host can also access the status registers of peripheral display device attached to TC358762XBG by issuing read commands. The read data is returned to host via DSI's reverse direction Low Power packets in Data Lane 0. Depending on the output I/F ports chosen; TC358762XBG can be configured to operate with various peripheral display devices. Features Standard followed: MIPI DSI version 1.01, Feb 2008 MIPI D-PHY version 0.9, Oct 2007 MIPI DPI version 2.0, Sep, 2005 MIPI DBI-2 version 2.00, Nov 2005 MIPI DCS Command version 1.02, Dec 2008 DSI Receiver Dual Data Lane DSI Link with Bi-direction support at Data Lane 0 Maximum speed at 800 Mbps/lane Video input data formats: RGB-565, RGB-666 and RGB-888 Video input frame rates: Up to 60 fps for WXGA (1366 x 768) Support various DSI packet types Provide the path for DSI host/transmitter to control TC358762XBG and its attached Display Device DPI Host Bus speed up to 75 MHz burst rate with data rate up to 216 Mbytes/s Support the following pixel formats: - RGB666 18 bit per pixel - RGB666 loosely packed 18 bit per pixel - RGB565 16 bit per pixel - RGB565 loosely packed 16 bit per pixel - RGB888 24 bit per pixel With the Toshiba Magic Square algorithm, an RGB666 18-bit or 16-bit LCD panel can produce a display equivalent to that of an (c) 2016-2017 Toshiba Electronic Devices & Storage Corporation RGB888 24-bit LCD panel with up to 16million colors Programmable output polarity Support up to frame size 1366 x 768 at 60 fps DBI Host Read/Write Data/Command from the external DBI slave device Support DCS commands, which is compliant with MIPI DBI-B standard Support Intel 80xx CPU I/F with either 8-bit or 16-bit commands Programmable Output Data Format and Bus Width - 8 bit Bus, RGB 565 (2 cycles/pixel) - 8 bit Bus, RGB 666 (3 cycles/pixel) - 8 bit Bus, RGB 888 (3 cycles/pixel) - 9 bit Bus, RGB 666 (2 cycles/pixel) - 16 bit Bus, RGB 565 (1 cycles/pixel) - 16 bit Bus, RGB 666 (3 cycles/2 pixel) note1 - 16 bit Bus, RGB 888 (3 cycles/2 pixel) note1 - 18 bit Bus, RGB 666 (1 cycles/pixel) - 24 bit Bus, RGB 888 (1 cycles/pixel) Support up to 864x480 at 60 fps (or 1280x720 at 30 fps) 1 / 22 2017-09-25 Rev.1.46 TC358762XBG SPI Master 4-pin SPI master I/F, CSX[1:0], CLK, DI and DO Support two SPI slaves Data Rate up to 10 Mbps The main purpose of this port is used to configure DPI slave display devices Half Duplex data transfer support DBI-C host 3-pin DBI-C host I/F, CSX, SCL and SDA Shared pins with SPI I/F, only one can be active at a given time Data Rate up to 10 Mbps Programmable read delay I2C compliant interface Slave Port Data Rate up to 400 kHz External I2C master can access TC358762XBG internal registers via this port Address auto increment is supported TC358762XBG Slave Port address is "0001011" During I2C slave cycle, DSI host must not transmit any new DSI packet to TC358762XBG. A 1024 x 24 dual port Video Buffer is used to buffer the video data received from DSI link. System Operation Register programming through DSI link via Generic Write Long packets. Register read through DSI link via Generic Read, 2 parameters packets. Write to WCMQUE and RCMDQUE registers enable host to configure and control peripheral display device DCS commands are routed to peripheral display device to interpret Provide Tearing Effect Trigger message after receiving set_tear_on command Power Consumption Sleep State - PLL OFF mode - Sleep mode (DSI-CLK stops toggle) IOs: 0.05 W CORE: 23 W D-PHYs: 3 mW PLLs: Off (PLL power - 0V) - PLL ON mode - Sleep mode (DSI-CLK goes to ULPS state, REFCLK toggles) IOs: 0.15 W CORE: 23 W D-PHYs: 9 W PLLs: 28 W Normal Operation: - PLLOFF mode (480x864 @60fps, DSI-CLK: 400 MHz - 2 data lanes) 18 mW PLLON mode (480x864 @60fps, DSI-CLK: 400 MHz, PLLCLK: 50.28MHz, PCLK=PLL/2) 19 mW Packaging BGA 64 pins 5.0mm x 5.0mm x 1mm 0.5mm ball pitch Clock source: External reference clock: recommended 6 - 40 MHz A programmable PLL is used to adjust the output video clock: - In DPI output mode with DSI link burst data, adjust output clock to the desired pixel clock frequency to assure no video is lost due to video buffer over/under flow. - In DBI output mode, adjust output clock frequency fast enough to prevent video buffer from over flow. Power supply MIPI D-PHY: 1.2V I/O: 1.8V - 3.3V (all IO pins must be same power level) Core: 1.2V (c) 2016-2017 Toshiba Electronic Devices & Storage Corporation 2 / 22 2017-09-25 Rev.1.46 TC358762XBG Table of content REFERENCES ..................................................................................................................................................... 6 1. Introduction....................................................................................................................................................... 7 2. Features ......................................................................................................................................................... 11 3. External Pins .................................................................................................................................................. 14 3.1. Pin Layout ................................................................................................................................................ 14 3.2. Pinout Description ................................................................................................................................... 15 4. Package ......................................................................................................................................................... 17 5. Electrical characteristics................................................................................................................................. 18 5.1. Absolute Maximum Ratings..................................................................................................................... 18 5.2. Operating Conditions ............................................................................................................................... 18 5.3. DC Electrical Specification ...................................................................................................................... 19 5.3.1. Normal CMOS I/Os ..................................................................................................................................................... 19 5.3.2. DSI Differential Inputs................................................................................................................................................. 20 5.3.2.1. Low power transmitter ...................................................................................................................................................20 5.3.2.2. High speed receiver ......................................................................................................................................................20 5.3.2.3. Low power receiver .......................................................................................................................................................20 6. Revision History ............................................................................................................................................. 21 RESTRICTIONS ON PRODUCT USE............................................................................................................... 22 Table of Figures Figure 1.1 Figure 1.2 Figure 1.3 Figure 1.4 Figure 3.1 Figure 4.1 TC358762XBG in System Application - Output with DPI and SPI Master .............................. 9 TC358762XBG in System Application - Output with DBI host only......................................... 9 TC358762XBG in System Application - Output with DBI and DBI-C host ............................ 10 TC358762XBG Functional I/Os and Block Diagram .............................................................. 10 TC358762XBG Chip Pin Layout (Top view) ........................................................................... 14 P-VFBGA64-0505-0.50BZ Package Dimension..................................................................... 17 List of Tables Table 1.1 Table 3.1 Table 3.2 Table 3.3 Table 5.1 Table 5.2 Table 5.3 Table 5.4 Table 5.5 Table 5.6 Table 6.1 Four Possible System Configurations........................................................................................ 7 TC358762XBG functional signal list ........................................................................................ 15 TC358762XBG Power signal list ............................................................................................. 16 Pin Count Summary ................................................................................................................. 16 Absolute Maximum Ratings ..................................................................................................... 18 Operating Conditions ............................................................................................................... 18 DC Electrical Specification - Normal CMOS IO ....................................................................... 19 MIPI DSI LP transmitter DC characteristics ............................................................................. 20 MIPI DSI HS receiver DC characteristics ................................................................................ 20 MIPI DSI LP receiver DC characteristics ................................................................................. 20 Revision History ....................................................................................................................... 21 3 / 22 2017-09-25 TC358762XBG HDMI is a trademark or registered trademark of HDMI Licensing, LLC in the United States and/or other countries. MIPI and SLIMbus are registered trademarks of MIPI Alliance, Inc. VESA, VESA logo and the DisplayPort Icon are trademarks of the Video Electronics Standards Association. 4 / 22 2017-09-25 TC358762XBG 1 2 3 4 5 6 7 8 9 NOTICE OF DISCLAIMER The material contained herein is not a license, either expressly or impliedly, to any IPR owned or controlled by any of the authors or developers of this material or MIPI. The material contained herein is provided on an "AS IS" basis and to the maximum extent permitted by applicable law, this material is provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIPI hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not limited to, any (if any) implied warranties, duties or conditions of merchantability, of fitness for a particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of viruses, and of lack of negligence. 10 11 12 13 14 All materials contained herein are protected by copyright laws, and may not be reproduced, republished, distributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express prior written permission of MIPI Alliance. MIPI, MIPI Alliance and the dotted rainbow arch and all related trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and cannot be used without its express prior written permission. 15 16 17 18 19 20 21 22 23 24 25 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET POSSESSION, CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT. IN NO EVENT WILL ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE GOODS OR SERVICES, LOST PROFITS, LOSS OF USE, LOSS OF DATA, OR ANY INCIDENTAL, CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER CONTRACT, TORT, WARRANTY, OR OTHERWISE, ARISING IN ANY WAY OUT OF THIS OR ANY OTHER AGREEMENT, SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL, WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. 26 27 28 29 30 31 32 33 34 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is further notified that MIPI: (a) does not evaluate, test or verify the accuracy, soundness or credibility of the contents of this Document; (b) does not monitor or enforce compliance with the contents of this Document; and (c) does not certify, test, or in any manner investigate products or services or any claims of compliance with the contents of this Document. The use or implementation of the contents of this Document may involve or require the use of intellectual property rights ("IPR") including (but not limited to) patents, patent applications, or copyrights owned by one or more parties, whether or not Members of MIPI. MIPI does not make any search or investigation for IPR, nor does MIPI require or request the disclosure of any IPR or claims of IPR as respects the contents of this Document or otherwise. 35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed to: 36 37 38 39 40 MIPI Alliance, Inc. c/o IEEE-ISTO 445 Hoes Lane Piscataway, NJ 08854 Attn: Board Secretary Copyright (c) 2005-2010 MIPI Alliance, Inc. All rights reserved. MIPI Alliance Member Confidential. All rights reserved. This material is reprinted with the permission of the MIPI Alliance, Inc. No part(s) of this document may be disclosed, reproduced or used for any purpose other than as needed to support the use of the products of Toshiba Cooperation and its subsidiaries and its affiliates 5 / 22 2017-09-25 TC358762XBG REFERENCES 1. 2. 3. 4. 5. MIPI D-PHY, "MIPI Alliance Specification for D-PHY Version 0.91.00 - r0.01 14-March-2008" MIPI Alliance Standard for DSI version 1.01, Feb 2008 MIPI Alliance Standard for DPI version 2.0, Sep, 2005 MIPI Alliance Standard for DBI-2 version 2.00, Nov 2005 MIPI Alliance Standard for DCS Command version 1.02, Dec 2008 6 / 22 2017-09-25 TC358762XBG Introduction This Functional Specification defines operation of a de-serializer chip, TC358762XBG. The serial data stream is supplied by the baseband processor via the DSI 1.01 interface. TC358762XBG chip de-serializes the stream into a parallel one. The parallel output bus can be either a DPI or a DBI bus. The usage of either DPI or DBI bus is mutually exclusive. The DSI host controls/configures TC358762XBG chip via DSI's Generic Long Write packets. The host controls (commands) the peripheral display device by sending DSI packets to TC358762XBG. TC358762XBG routes the commands either through DBI host, SPI master or DBI-C host interface, I/F, block to the peripheral device. TC358762XBG supports both DCS and generic commands. The commands output through these interfaces are intended for the peripheral display device to interpret and execute; TC358762XBG does not interpret them, except a few DCS commands mentioned explicitly in this document. TC358762XBG supports bi-directional DSI link. The host reads TC358762XBG's registers via DSI's Generic Read (2 parameter) packets. Host can also access the status registers of peripheral display device attached to TC358762XBG by issuing read commands. The read data is returned to host via DSI's reverse direction Low Power packets in Data Lane 0. Depending on the output I/F ports chosen; TC358762XBG can be configured to operate with various peripheral display devices. Four possible system configurations are listed in Table 1.1. Table 1.1 Four Possible System Configurations Mode Pin MD[1:0] Config 1 DPI Config 2 CPU Config 3 DBI-B Config 4 DBI-B/C 2'b10 Command Input I/F 2'b00 2'b01 I2C Bus or DSI Link Command Input Format Video Input Packet Command Output I/F Generic Commands SPI Master (Loosely) Packed Pixel Stream DBI Host DCS Commands DCS Long Write Video Output I/F DPI Host DBI Host DBI-C Host 1. Configuration 1, Figure 1.1: DPI Mode: MD[1:0] pins are set to 2'b00 note1. DPI host (I/F block) is used to output video data. SPI master is chosen for transferring commands to the peripheral device. An external I2C master configures TC358762XBG via the I2C slave port. It can also issue commands to peripheral display device by writing to TC358762XBG register WCMDQUE or RCMDQUE for write or read commands, respectively Note4. The external I2C master can assert register bit SLEEP to put TC358762XBG in sleep mode. During the sleep mode, TC358762XBG shuts down all its internal blocks to consume minimum amount of power. DSI link operates in either burst or non-burst mode with sync pulses; DSI host is responsible for generating all the timing required packets. TC358762XBG expects Vsync Start, Vsync End, Hsync Start and Hsync End packets from DSI host in order to run video data synchronously with DSI host. 2. Configuration 2, Figure 1.2: CPU Mode: MD[1:0] pins are tied to 2'b01 note2, Generic Commands are expected. In this mode, both video data and commands are routed to DBI host I/F. This mode supports LCD device drivers with Intel 80xx CPU I/F. Commands and their parameters can be either 8-bit or 16-bit in width, depending on the setting in register bit APLCNTL[CMD16]. In 16-bit command mode, both the command and its parameters are expected to be 16-bit aligned. The unused byte should be filled with "0s". Video data are expected in Pixel Stream Packets. 7 / 22 2017-09-25 TC358762XBG 3. Configuration 3, Figure 1.2: DBI-B Mode: MD[1:0] pins are tied to 2'b01 note2, note3, DCS Command Packets are used. In this mode, both video data and commands are routed to DBI host I/F. TC358762XBG switches to this mode when DCS Command Packets are received from DSI link. Only DCS commands are expected in this mode to communicate with peripheral display device, the command bus is set to be 8-bit, independent of register bit APLCNTL[CMD16]. 4. Configuration 4, Figure 1.3: DBI-B/C Mode: MD[1:0] pins need to be 2'b10 note2. DBI host is used to output video data; DBI-C host is chosen to communicate with the peripheral device. DSI host uses Generic Long Write packets to configure TC358762XBG and issues DCS command to communicate with peripheral device. In addition, the initialization of TC358762XBG could be done by the display system, too. After detecting the assertion of its interrupt, INTX (active low), pin driven by the peripheral display device; TC358762XBG starts DBI-C host read cycles to fetch desired configurations from the peripheral display device. PWDNX is an active low output signal, which is used to turn off the DC power supplier to the display system as shown in Figure 1.3. TC358762XBG asserts/de-asserts PWDNX after receiving "enter_sleep_mode/exit_sleep_mode" command from DSI host. After asserting PWDNX, DSI host is expected to signal ULPS to put TC358762XBG into sleep mode. During this period, TC358762XBG shuts down the power of all the blocks while keeping DSI Rx port running in order to be woken up by detecting ULPS to LP transition on the DSI link. The peripheral display device also provides a TE input to TC358762XBG, which is used with DCS commands set_tear_on/off to perform video line/frame timing synchronization. DSI host can burst the video data on the link up to one video frame if it sets TC358762XBG's DBI output clock to fetch data faster than DSI link input data rate. The following handshake is required at the beginning of each frame before the TC358762XBG starts sending video data out in DBI-B/C mode: After receiving DCS command write_memory_start, TC358762XBG pulls down INTX pin for 5 pixel clock cycles and releases it to indicate the start of new frame. When the peripheral device is ready to accept the new frame of data, it pulls down INTX signal for 5 cycles. After detecting the falling edge of INTX, TC358762XBG starts pumping data out at DBI port. Only DCS Command Packets are expected in this mode. Note1: Note2: Note3: Note4: In DPI mode, there are other possible configurations, e.g.: DSI data can be burst, bi-directional DSI link is enabled or DBI-C could be chosen to interface with the peripheral display device. Configuration 2, 3 and 4 use DBI host to output video data. They might be referred as DBI modes in this document if it does not cause any ambiguity. Both CPU and DBI-B modes use the same pins. DBI-B mode uses DCS commands as specified in MIPI DBI-B standard. CPU mode uses generic commands which follows Intel 80xx CPU I/F specification. When I2C master access to TC358762XBG, DSI Host must not transmit any new DSI packet to TC358762XBG until I2C access is completed. 8 / 22 2017-09-25 TC358762XBG The inputs/outputs and high level block diagram of TC358762XBG chip is depicted in Figure 1.4. Note: BB in the next four figures could be a Baseband or Application Processor. ~46 MHz @ 20% Blank D-PHY (Clock) MIPI-DSI Dual Lane BB D-PHY (Data 1) DSI Rx PPI DSI Rx Protoc. DSI Rx Appl. D-PHY (Data0) ~ 820 Mbps @24 bit, 60 fps Over Head 10% LCDC (Timing Gen. Magic Square) Video Buffer ~41 MHz @ 10% Blank DPI 24bit Main LCD GPIO0 LCDD PLL System Ctrl (clkgen, Iomux, Test) MD[1:0] DPI / DBI Host RESX Register SPI Master BM Cntl I2C Slave DPI Panel Up to 960 x 540 Panel @60 fps I2C Data Path Supply Voltage I/O: 1.8 V Core : 1.2 V DSI-Rx: 1.2 V Control Path Figure 1.1 TC358762XBG in System Application - Output with DPI and SPI Master LCDC (Timing Gen. Magic Square) D-PHY (Clock) MIPI-DSI Dual Lane BB D-PHY (Data 1) DSI Rx PPI DSI Rx Protoc. DSI Rx Appl. Video Buffer ~37 MHz @ 20% Blank ~34 MHz @ 10% Blank DBI 24bit Main LCD D-PHY (Data0) ~ 820 Mbps @24 bit, 60 fps Over Head 10% LCDD PLL REFCLK Register System Ctrl (clkgen, Iomux, Test) MD[1:0] BM Cntl RESX Supply Voltage I/O: 1.8 V - 3.3 V Core : 1.2 V DSI-Rx: 1.2 V Figure 1.2 DPI / DBI Host SPI Master DBI Panel I2C Slave Up to 960 x 540 Panel @60 fps Data Path Control Path TC358762XBG in System Application - Output with DBI host only 9 / 22 2017-09-25 TC358762XBG D-PHY (Clock) DSI Rx Protoc. LCDC (Timing Gen. Magic Square) DSI Rx Appl. ~ 660 Mbps @24 bit, 60 fps Over Head 10% ~28 MHz DBI-B 24 bit D-PHY (Data0) Display Device TE PLL REFCLK System Ctrl (clkgen, Iomux, Test) MD[1:0] Register DBI-C Master BM Cntl I2C Slave RESX Supply Voltage I/O: 1.8 V - 3.3 V Core : 1.2 V DSI-Rx: 1.2 V Drive Up to 864 x 480 Panel @60fps DPI/ DBI Host Video Buffer D-PHY (Data 1) MIPI-DSI Dual Lane BB DSI Rx PPI INTX PWDNX EN Display DC Supply Data Path Control Path Figure 1.3 DSCP DSCM DSD0P DSD0M DSD1P DSD1M REFCLK TC358762XBG in System Application - Output with DBI and DBI-C host D-PHY (Clock) D-PHY (Data0) DSI Rx PPI DSI Rx Protoc. D-PHY (Data1) DSI Rx Appl. LCDC (Timing Gen. Magic Square) VD/MDATA[23:0] Video Buffer PLL Register MD[1:0] PWDNX RESX System Ctrl (clkgen, Iomux, Test) Figure 1.4 DPI / DBI Host VSYNC/MDCX HSYNC/MCSX DE/MRDX DCLK/MWRX BM Cntl SPI/ DBI-C Master I2C Slave TE/SPI_CSX1 SPI_CSX0/DBIC_CSX SPI_CLK/DBIC_SCL SPI_DO/DBIC_SDA SPI_DI/INTX I2C_SCL I2C_SDA TC358762XBG Functional I/Os and Block Diagram 10 / 22 2017-09-25 TC358762XBG Features Standard followed: MIPI DSI version 1.01, Feb 2008 MIPI D-PHY version 0.9, Oct 2007 MIPI DPI version 2.0, Sep, 2005 MIPI DBI-2 version 2.00, Nov 2005 MIPI DCS Command version 1.02, Dec 2008 DSI Receiver Dual Data Lane DSI Link with Bi-direction support at Data Lane 0 Maximum speed at 800 Mbps/lane Video input data formats: RGB-565, RGB-666 and RGB-888 Video input frame rates: Up to 60 fps for WXGA (1366 x 768) Support various DSI packet types Provide the path for DSI host/transmitter to control TC358762XBG and its attached Display Device DPI Host Bus speed up to 75 MHz burst rate with data rate up to 216 Mbytes/s Support the following pixel formats: - RGB666 18 bit per pixel - RGB666 loosely packed 18 bit per pixel - RGB565 16 bit per pixel - RGB565 loosely packed 16 bit per pixel - RGB888 24 bit per pixel With the Toshiba Magic Square algorithm, an RGB666 18-bit or 16-bit LCD panel can produce a display equivalent to that of an RGB888 24-bit LCD panel with up to 16-million colors Programmable output polarity Support up to frame size 1366 x 768 at 60 fps DBI Host Read/Write Data/Command from the external DBI slave device Support DCS commands, which is compliant with MIPI DBI-B standard Support Intel 80xx CPU I/F with either 8-bit or 16-bit commands Programmable Output Data Format and Bus Width - 8 bit Bus, RGB 565 (2 cycles/pixel) - 8 bit Bus, RGB 666 (3 cycles/pixel) - 8 bit Bus, RGB 888 (3 cycles/pixel) - 9 bit Bus, RGB 666 (2 cycles/pixel) - 16 bit Bus, RGB 565 (1 cycles/pixel) - 16 bit Bus, RGB 666 (3 cycles/2 pixel) note1 - 16 bit Bus, RGB 888 (3 cycles/2 pixel) note1 - 18 bit Bus, RGB 666 (1 cycles/pixel) - 24 bit Bus, RGB 888 (1 cycles/pixel) Support up to 864x480 at 60 fps (or 1280x720 at 30 fps) Note 1: When this format is selected, the horizontal image size must be multiple of four. 11 / 22 2017-09-25 TC358762XBG SPI Master 4-pin SPI master I/F, CSX[1:0], CLK, DI and DO Support two SPI slaves Data Rate up to 10 Mbps The main purpose of this port is used to configure DPI slave display devices Half Duplex data transfer support DBI-C host 3-pin DBI-C host I/F, CSX, SCL and SDA Shared pins with SPI I/F, only one can be active at a given time Data Rate up to 10 Mbps Programmable read delay I2C compliant interface Slave Port Data Rate up to 400 kHz External I2C master can access TC358762XBG internal registers via this port Address auto increment is supported TC358762XBG Slave Port address is "0001011" During I2C slave cycle, DSI host must not transmit any new DSI packet to TC358762XBG. A 1024 x 24 dual port Video Buffer is used to buffer the video data received from DSI link. System Operation Register programming through DSI link via Generic Write Long packets. Register read through DSI link via Generic Read, 2 parameters packets. Write to WCMQUE and RCMDQUE registers enable host to configure and control peripheral display device DCS commands are routed to peripheral display device to interpret Provide Tearing Effect Trigger message after receiving set_tear_on command Clock source: External reference clock: recommended 6 - 40 MHz A programmable PLL is used to adjust the output video clock: - In DPI output mode with DSI link burst data, adjust output clock to the desired pixel clock frequency to assure no video is lost due to video buffer over/under flow. - In DBI output mode, adjust output clock frequency fast enough to prevent video buffer from over flow. Power supply MIPI D-PHY: 1.2V I/O: 1.8V - 3.3V (all IO pins must be same power level) Core: 1.2V 12 / 22 2017-09-25 TC358762XBG Power Consumption Sleep State - PLL OFF mode - Sleep mode (DSI-CLK stops toggle) IOs: 0.05 W CORE: 23 W D-PHYs: 3 mW PLLs: Off (PLL power - 0V) - PLL ON mode - Sleep mode (DSI-CLK goes to ULPS state, REFCLK toggles) IOs: 0.15 W CORE: 23 W D-PHYs: 9 W PLLs: 28 W Normal Operation: - PLLOFF mode (480x864 @60fps, DSI-CLK: 400 MHz - 2 data lanes) 18 mW PLLON mode (480x864 @60fps, DSI-CLK: 400 MHz, PLLCLK: 50.28MHz, PCLK=PLL/2) 19 mW Packaging BGA 64 pins 5.0mm x 5.0mm x 1mm 0.5mm ball pitch Note: Attention about ESD. This product is weak against ESD. Please handle it carefully. 13 / 22 2017-09-25 TC358762XBG External Pins 3.1. Pin Layout The mapping of TC358762XBG signals to the external pins is shown in the figure below. A1 A2 A3 A4 A5 A6 A7 A8 DSD0P RESX VSSC DCLK VD01 VD02 VD04 VD05 B1 B2 B3 B4 B5 B6 B7 B8 DSD0M PWDNX VDDC VSYNC VD00 VSSO VDDS VD06 C1 C2 C3 C4 C5 C6 C7 C8 DSCP MD0 MD1 HSYNC VD20 VD03 VD07 VSSC D1 D2 D3 D4 D5 D6 D7 D8 DSCM VSSA VDDS DE VD21 VSSO VD08 VD09 E1 E2 E3 E4 E5 E6 E7 E8 DSD1P VSSC SPI_CSX1 VSSO VD22 VDDC VD11 VD10 F1 F2 F3 F4 F5 F6 F7 F8 DSD1M I2C_SCL SPI_CSX0 SPI_DI VD23 VD16 VDDS VSSO G1 G2 G3 G4 G5 G6 G7 G8 VDDA I2C_SDA VDDPL VSSO VD19 VSSO VD14 VD12 H1 H2 H3 H4 H5 H6 H7 H8 VSSPL REFCLK SPI_DO SPI_CLK VD18 VD17 VD15 VD13 Figure 3.5 TC358762XBG Chip Pin Layout (Top view) Pin Name Abbreviation: VSYNC (B4): VSYNC/MDCX HSYNC (C4): HSYNC/MCSX DE (D4): DE/MRDX DCLK (A4): DCLK/MWRX VDn (n=0 to 23): VD[23:0]/MDATA[23:0] SPI_CSX0 (F3): SPI_CSX0/DBIC_CSX/GPIO3 SPI_CLK (H4): SPI_CLK/DBIC_SCL/GPIO2 SPI_DO (F3): SPI_DO/DBIC_SDA/GPIO1 SPI_DI (F4): SPI_DI/INTX/ SPI_CSX1(E3): SPI_CSX1/TE/GPIO4 14 / 22 2017-09-25 TC358762XBG 3.2. Pinout Description The following table gives the signals of TC358762XBG and their function. Table 3.2 TC358762XBG functional signal list Group Pin Name Pin Type No. Buffer Type RESX REFCLK A2 H2 I I SCH SCH PWDNX B2 O N MD[1:0] C2 C3 I N C1 D1 A1 B1 E1 F1 I I I/O I/O I I MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY MIPI-PHY B4 O Nps C4 O Nps D4 O Nps A4 O Nps - I/O Nps System MIPI-DSI DPI/ DBI SPI/ DBI-C/ Misc. DSCP DSCM DSD0P DSD0M DSD1P DSD1M VSYNC/ MDCX HSYNC/ MCSX DE/ MRDX DCLK/ MWRX VD[23:0]/ MDATA[23:0] SPI_CSX0/ DBIC_CSX/ GPIO3 F3 I/O N SPI_CLK/ DBIC_SCL/ GPIO2 H4 I/O N SPI_DO/ DBIC_SDA/ GPIO1 H3 I/O N SPI_DI/ INTX/ GPIO0 F4 I/O N SPI_CSX1/ TE/ GPIO4 E3 I/O N 15 / 22 Function Power Supply System Reset - active Low 6MHz - 40MHz Reference Clock Power Down signal (active low) H L: TC358762XBG enter Power down state L H : TC358762XBG exit Power down state Mode selection 00: DPI mode 01: CPU or DBI-B mode 10: DBI-B/C mode 11: Test mode MIPI-DSI clock channel positive MIPI-DSI clock channel negative MIPI-DSI Data 0 channel positive MIPI-DSI Data0 channel negative MIPI-DSI Data 1 channel positive MIPI-DSI Data 1 channel negative DPI i/f: Vsync signal DBI i/f: Data/Command signal DPI i/f: Hsync signal DBI i/f: Chip Select signal DPI i/f: Data Enable signal DBI i/f: Read Command signal DPI i/f: Clock signal DBI i/f: Write Command signal 1.8V-3.3V 1.8V-3.3V VD[23:0] : 24-bit video data 1.8V-3.3V DPI i/f: GPIO3 signal(default) or SPI Chip Select signal DBI i/f: GPIO3 signal DBI-B/C i/f: DBI-C Chip Select signal DPI i/f: GPIO2 signal(default) or SPI Clock signal DBI i/f: GPIO2 signal DBI-B/C i/f: DBI-C Clock signal DPI i/f: GPIO1 signal(default) or SPI Output Data signal DBI i/f: GPIO1 signal DBI-B/C i/f: DBI-C Data signal DPI i/f: GPIOI0 signal(default) or SPI Input Data DBI i/f: GPIO0 signal DBI-B/C i/f: INTX signal DPI i/f: GPIO4 signal(default) or SPI_CSX1 signal DBI i/f: TE signal DBI-B/C i/f: TE signal 1.8V-3.3V 1.8V-3.3V 1.2V 1.2V 1.2V 1.2V 1.2V 1.2V 1.8V-3.3V 1.8V-3.3V 1.8V-3.3V 1.8V-3.3V 1.8V-3.3V 1.8V-3.3V 1.8V-3.3V 1.8V-3.3V 1.8V-3.3V 2017-09-25 TC358762XBG I2C POWER & GROUND I2C_SCL F2 I S-OD I2C_SCL signal 1.8V-3.3V I2C_SDA G2 I/O S-OD 1.8V-3.3V See table below I2C_SDA signal Notes: if I2C i/f is not use, must pull LOW on this signal. - - - - - Table 3.3 TC358762XBG Power signal list PWR & GND PINS POWER GROUND PIN NAME PIN NO VDDC VDDS VDDPL VDDA VSSA VSSPL VSSC VSSO (2) (3) (1) (1) (1) (1) (3) (6) PIN DESCRIPTION VDD for Internal Core VDD for IO power supply VDD for PLL VDD for MIPI-DSI PHY VSS for MIPI-DSI PHY VSS for PLL Core VSS IO VSS Power Supply Voltage 1.2V 1.8V-3.3V 1.2V 1.2V - Buffer Type Abbreviation: N: Normal IO (2mA) Nps: Normal IO with Programmable Output Strength (1/2/3/4 mA) S-OD: Pseudo open-drain output, schmitt input SCH: Fail Safe schmitt input buffer MIPI-PHY: front-end analog IO for MIPI APAD: Analog pad Table 3.4 Pin Count Summary Group Name Pin Count Notes SYSTEM MIPI-DSI DPI/DBI SPI/DBI-C/Misc. I2C POWER & GROUND Total Pin Count 5 6 28 5 2 18 64 - 16 / 22 2017-09-25 TC358762XBG Package TC358762XBG housed in a P-VFBGA64-0505-0.50BZ package (5 mm by 5 mm size), 0.5mm ball pitch. The detailed package drawing is shown below. Weight: 41 mg (Typ.) Figure 4.6 P-VFBGA64-0505-0.50BZ Package Dimension 17 / 22 2017-09-25 TC358762XBG Electrical characteristics 5.1. Absolute Maximum Ratings Operating ambient Temperature range: Ta = -20C - +85C All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Table 5.5 Absolute Maximum Ratings Parameter Supply voltage (1.8V-3.3V - Digital IO) Supply voltage (1.2V - Digital Core) Supply voltage (1.2V - MIPI DSI PHY) Supply voltage (1.2V - PLL) Input voltage (DSI I/O) Input voltage (Digital IO) Junction temperature Storage temperature Symbol Rating Unit VDDS -0.3 to +3.9 V VDDC -0.3 to +2.0 V VDDA -0.3 to +2.0 V VDDPL -0.3 to +2.0 V VIN_DSI -0.3 to VDDA+0.3 V VIN_IO -0.3 to VDDS+0.3 V Tj Tstg 125 -40 to +125 C C 5.2. Operating Conditions Table 5.6 Operating Conditions Parameter Supply voltage (1.8V - Digital IO) Supply voltage (3.3V - Digital IO) Supply voltage (1.2V - Digital Core) Supply voltage (1.2V - PLL) Supply voltage (1.2V - MIPI-DSI PHY) Operating temperature (ambient temperature with voltage applied) Symbol Min Typ. Max Unit VDDS VDDS VDDC VDDPL 1.65 3.0 1.1 1.1 1.8 3.3 1.2 1.2 1.95 3.6 1.3 1.3 V V V V VDDA 1.12 1.2 1.28 V Ta -20 - +85 C 18 / 22 2017-09-25 TC358762XBG 5.3. DC Electrical Specification All typical values are at normal operating conditions unless otherwise specified. 5.3.1. Normal CMOS I/Os Table 5.7 DC Electrical Specification - Normal CMOS IO Parameter - CMOS I/Os Input voltage, High level CMOS input Note1 Input voltage, Low level CMOS input Note1 Input voltage High level CMOS Schmitt Trigger Symbol Min Typ. Max Unit VIH 0.7 VDDS - VDDS V VIL 0 - 0.3 VDDS V VIHS 0.7 VDDS - VDDS V VILS 0 - 0.3 VDDS V VOH 0.8 VDDS - VDDS V VOL 0 - 0.2 VDDS V IILH (Note3) IILL (Note4) -10 -10 - 10 10 A A Note 1,2 Input voltage Low level CMOS Schmitt Trigger Note 1,2 Output voltage, High level Note1, 2 Output voltage, Low level Note1, 2 Input leakage current, High level Input leakage current, Low level Note1: Note2: Note3: Note4: Each power source is operating within recommended operating condition. Current output value is specified to each IO buffer individually. Output voltage changes with output current value. VOH, VOL values above are specification when current, which is defined in type column of Table 3.1, flows at corresponding I/O pin. Normal pin or Pull-up I/O pin applied VDDS supply voltage to Vin (input voltage) Normal pin or Pull-down I/O pin applied VSS (0V) to Vin (input voltage) 19 / 22 2017-09-25 TC358762XBG 5.3.2. DSI Differential Inputs 5.3.2.1. Low power transmitter The low power transmitter is used for driving the lines in all low-power operating modes. The DC characteristics of the LP transmitter are given below. Table 5.8 MIPI DSI LP transmitter DC characteristics Parameter Symbol Min Typ. Max Unit VOH VOL ZOLP 1.1 -50 110 1.2 - 1.3 50 - V mV Thevenin output high level Thevenin output low level Output impedance of the LP transmitter 5.3.2.2. High speed receiver The HS receiver is a differential line receiver with a switch able parallel input termination. It will be used to receive data during high speed transmission from the host. The DC characteristics of the HS receiver are given below. Table 5.9 MIPI DSI HS receiver DC characteristics Parameter Symbol Min Typ. Max Unit VCMRX(DC) 70 - 330 mV Differential input high threshold VIDTH - - 70 mV Differential input low threshold Single-ended input high voltage Single-ended input low voltage VIDTL VIHHS VILHS -70 -40 - 460 - mV mV mV VTERM-EN - - 450 mV ZID 80 100 125 Common-mode voltage HS receive mode Single-ended threshold for HS termination enable Differential input impedance 5.3.2.3. Low power receiver The LP receiver is used to detect the Low-Power state on each pin. The LP will be used to receive data during low speed transmission from the host. The DC characteristics of the LP receiver are given below. Table 5.10 MIPI DSI LP receiver DC characteristics Parameter Logic 1 input voltage Logic 0 input voltage, not in ULP state Logic 0 input voltage, ULP state Input hysteresis Symbol Min VIH VIL 880 25 VIL-ULPS VHYST 20 / 22 Typ. - Max 550 300 - Unit mV mV mV mV 2017-09-25 TC358762XBG Revision History Table 6.11 Revision History Revision Date Description 1.412 2016-04-01 1.412 2016-04-01 1.45 2016-06-03 Added Figure 1.1. Updated Figure 1.4 to have I2C_SCL as input. Changed D6 pin name of Figure 3.1. 1.46 2017-09-25 Modified PIN NO of Table 3.2. Changed header, footer and the last page. Changed corporate name and descriptions. Newly released Package's weight is rounding up digits after the decimal point to form an integer. 21 / 22 2017-09-25 TC358762XBG RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as "TOSHIBA". Hardware, software and systems described in this document are collectively referred to as "Product". * TOSHIBA reserves the right to make changes to the information in this document and related Product without notice. * This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission. * Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS. * PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT ("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. IF YOU USE PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your TOSHIBA sales representative. * Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part. * Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. * The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. * ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT. * Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). Product and related software and technology may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. * Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS. 22 / 22 2017-09-25