APR 2.0 198% PUMA 3F8003-15/17/20 Issue 1.0 : March 1991 ADVANCE PRODUCT INFORMATION motaic Mosaic Semiconductor ~ ine 8,388,608 bit CMOS FLASH Memory Module (pin Definition Features Fast access times of 150/170/200 ns Utilizes 66 PGA FR4 epoxy substrate User Configurable as 32 / 16 / 8 bit wide output Operating Power 200 / 110 / 65 mW (typical) Low Power Standby 1 mW (typical) Single High Voltage for Erase/Write : V,,=12.0V+5% Fast Programming - Byte =10us, Module = 4 sec. (typ) Flash Electrical Erase of Module 2 seconds typ 10* Erase/Write Cycle Endurance min. (10 typical) Uses Command Register Architecture for all operations On board decoupling capacitors 12 VIEW FROM ABOVE Block Diagram AO-A17 OE Wea WES Wee WE1 COoO0O0 000000 Of- BIO0O0O0O0000000 BIO COCO COOCOO OF8 EIOOOOO0O0 COO OF FiooooOooooo oO Og SIOOCOOOOOCO 0 OF _ _ For pinout see page 11 Pin Functions A0-A17 Address Inputs DO-D31 Data Input/Output CS1-4 Chip Selects OE Output Enable WE1-4 = Write Enables 256K x8| |256K x8] |256K x8] |256K x8 sme1 | [-sme2..| | osmes-=| | sea. Vpp es Vpp Write/Erase input Voltage eer Voc Power (+5V) DO-7 8-15 L GND ~~ Ground y D16-23 D24-31 (Package Details Dimensions in mm (inches). >) 2.54 15.20 (0.600) typ Oo. PI 5 a: 4 IDENT ou 8 = to oe ro o 9 o e o o e o o t) L 5.50 (0.216) max| 4 ~T}1 4.50 (0.060)ISSUE 1,0 : MARCH 1991 GENERAL DESCRIPTION The PUMA 2F8003 is a 8,388,608 bit CMOS FLASH Memory which is configurable as 8, 16 or 32 bit wide output using CS1-4, allowing flexibillty in a wide range of applications. FLASH memory combines the functionality of EPROM with on-board electrical Write/Erasure. The PUMA 2F8003 utilises devices which use a Command Regis- ter to manage these functions, allowing fixed power supply during Write/Erase and maximum EPROM PUMA 2F8003-17/20/25 compatibilty. During Write cycles, the command regis- ter internally latches address and data needed for the Write and Erase operations, thus simplifying the exter- nal control circuitry. FLASH technology reliably stores data even after 10,000 Write/Erase cycles and utilises a single pro- gram supply of 12V+5%. Additionally, the interactive program algorithm allows a typical room temperature program time of 4 seconds for the entire module (in 32 bit mode). The typical module erasure time is less than 10 seconds. Absolute Maximum Ratings Temperature Under Bias T Storage Temperature Tero Voltage on Any Pin with respect toGND@ V,, Voltage on AQ pin with respecttoGND = V,, Voltage on V,, pin with respect toGND ~~ V,, Voc Supply Voltage Voc Output Short Circuit Current Isc Notes : (1) -55 to +125 C -65 to +150 C -2.0 to +7.0 V -2.0t0 13.5 V -2.0 to +14.0 V -2.0to +7.0 V 100 mA Stresses above those listed may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci- fication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) Minimum DC input voltage is -0.5V. During transition s inputs may undershoot to -2.0V for periods less than 20 ns. Maximum DC voltage on output pins is V,,+0.5V, which may overshoot to V,.+2.0V for periods less than 20 ns. (3) Minimum DC input voltage is -0.5V. During transition s inputs may undershoot to -2.0V for periods less than 20 ns. Maximum DC input voltage is +13.5V, which may overshoot to +14.0V for periods less than 20 ns. (4) Output shorted for no more than one second. No more than one output shorted at any one time. Recommended Operating Conditions min typ max Supply Voltage Voc 45 5.0 5.5 Vv Programming Voltage Read V,,, -0.5 5.0 126 V Write/Erase/Verify Voow 11.4 12.0 126 V Input High Voltage TTL Vy, 2.0 - Veet 0.5 V CMOS Vi. 0.7 Veg - Voot0.5 V Input Low Voltage TTL Vy -0.5 - 0.8 Vv CMOS Vic -0.5 - 0.8 Vv Operating Temperature T, 0 - 70 C Ta, -40 - 85 C (-l suffix) Tam -55 - 125 C (-M,-MB suffix) Capacitance (T,=25C,f=1MHz) Parameter Symbol Test Condition typ max Unit Input Capacitance Address,OE Cy, Vyz0V - 24 pF Vop Cn Viy=OV - 24 pF Otherpins Cy, Vy=OV - 6 pF Output Capacitance 32 bit Corras Voy1= OV - 12 pF W6bit Corn, Voyr=0V - 24 pF B8bit C Voyr=0V - 48 pF OUT8 Note: These parameters are calculated, not measured.PUMA 3F6003- 15/17/20 (SSUE 1.0 : MARCH 1991 DC Electrical Characteristics (T,=-40C to +85C,V,,=5V + 10%) Parameter Symbol Test Condition min typ? max Unit VP Leakage Current Address,OE $4, 9 Voc=Vec MAX VineOV Or VecVpp=Ver, - +4 pA Other Pins |, Voc=Veo MAX, Viy=OV OF Vee - - +1 pA Output Leakage Current lo Voc=Veo MAX, Voyr= OV OF Voc: 8 bit - - +40 WA Vap Read Current lop) Vpp=Vern - 270 800 WBA Device Identifier Current ly AQ=V,, - 270 800 WA Veg Operating Current 32 bit Iogogy CS=V i, OE = Vip Lou OmA, f-6MHZ - 40 120 mA 16 bit loco AS above - 22 62 mA Bbit logo, As above - 13 33. mA Vog Programming Current 32 bit Ioopg9 Programming in Progress - 4 40 mA 16 bit Ioop4, As above - 4 22 mA Bbit loop, As above - 4 13. mA Vog Erase/Verify Current 32 bit loge CS=V,""), Write/Erase in progress - 20 60 mA 16 bit |ooc,g As above - 12 32 mA Bbit loge, As above - 8 18 mA Vop Write/Erase Current 32 bit Iopa2 Vep=Verne Write/Erase in progress - 40 120 mA 16 bit 1,,,, As above - 22 62 mA Bbit laos As above - 13 33. mA Standby Supply Current TTL lea, Vec=Vee max. CS=V,," - - 4 mA CMOS leas Vec=Vee Max, CS=Vyyc" - 200 400 wpA Device Identifier Voltage Vip AI=Vio 11.5 - 13.0 V Vpp Voltage During Read Only V,,, Write/Erase Inhibited if V,.=Vpp, 0 - 65 %V Read/Write. Vo, - 11.4 - 126 V Output Low Voltage "Vo lgp=2-1mA. ' - - 045 V Output High Voltage TTLioading Vo, loy=-2-5mA. 2.4 - - V CMOS loading Voy. Ioy=- TOOHA. Vog70.4 - WV Notes (1) GS above are accessed through CS1-4. These inputs must be operated simultaneoulsy for 32 bit operation, in pairs in 16 bit mode and singly for 8 bit mode. (2) Typical figures are measured at 25C and nominal V,. (3). Maximum active current is the sum of lecllep) and I... . (4) CAUTION: the PUMA 3F8003 must not be removed from or inserted into a socket when V,, OF Vep is applied. ERASE AND PROGRAMMING PERFORMANCE Parameter min typ max Units Comments Erase Times 32 bit - 2 30 sec Excludes 00,, Programming Prior to Erasure Program Times 32 bit - 4 25 sec Excludes System-Level Overhead Write/Erase Cycles 10* 10. - cycles Not 100% tested AC Test Conditions * Input pulse levels: 0.45V to 2.4V. * Input rise and fall times: < 10ns. * Input and Output timing reference levels: 0.8V and 2.0V * Output load : 1 TTL gate plus 100 pF.ISSUE 1.0 : MARCH 1991 PUMA 3F8003-15/17/20 READ AC Characteristics -15 -17 -20 Parameter Symbol min max min max min max Unit Read Cycie Time i 150 - 170 - 200 - ns Chip Select Access Time tes - 150 - 170 - 200 ns Address Access Time troc - 150 - 170 - 200 ns Output Enable Access Time toe - 50 - 50 - 55 ns Chip Select to Output in Low Z@ ty 0 - 0 - 0 - ns Output Enable to Output inLow Z) t,., 0 - 0 - 0 - ns Output Disable to Output in High 2" t,, - 35 - 40 - 40 ns Output Hold Time tou 0 - 0 - 0 - ns Write Recovery Time twuet 6 - 6 - 6 - ys Notes: (1) t,, is defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. (2) These parameters are sampled and not 100% tested. (3) The 150ns part is not available over Industrial temperature range. Read Cycle Timing Waveform POWER DEVICE AND uP STANOBY ADORESS SELECTION OUTPUTS ENABLED DATA VALID STANDBY POWER DOWN Address ADDRESS STABLE tac lacc vs y, OF / WE tou DATA OUTPUT VALID Voc JPUMA 3F8003-15/17/20 ISSUE 1.0 : MARCH 1991 WRITE/ERASE/PROGRAM " AC Characteristics -15 -17 -20 Parameter Symbol min max min max min max Unit Write Cycle Time twe 150 - 170 - 200 - ns Address Setup Time tas 0 - 0 - 0 - ns Address Hold Time tay 60 - 60 - 60 - ns Data Setup Time tos 50 - 50 - 50 - ns Data Hold Time toy 10 - 10 - 10 - ns Write Recovery Time twueL 6 - 6 - 6 - bs Read Recovery Time teuwe 0 - 0 - 0 - ps Chip Select Setup Time tes 20 - 20 - 20 - ns Chip Select Hold Time ton 0 - 0 - 0 - ns Write Pulse Width twp 50 - 50 - 50 - ns Write Pulse Width High tweu 20 - 20 - 20 - ns Duration of Programming Operation tywiayi, 10 25 10 25 10 25 Ls Duration of Erase Operation Www 9-9 10.5 9.5 10.5 9.5 10.5 ms Vpp Setup Time to Chip Select Low type, 100 - 100 - 100 - ns Veg Setup Time tyes 2 - 2 - 2 - ys Vpp Rise Time typpp 900 - 500 - 500 - ns Vpp Fall Time typpp 00 - 500 - 500 - ns Notes (1) Read timing characteristics during read/write operations are the same as during read only operations. Refer to AC Characteristics for read only operations. (2) The 150ns part is not available over Industrial temperature range. Programming Timing Waveform - POWER UP SET.UP PROGRAM PROGRAM COMMAND LATCH PROGRAMMING VERY COMUAND PROGRAM VERIFICATION DATA DATAW = 40, DATA WN = COnISSUE 1.0 : MARCH 1991 PUMA 3F8003- 15/17/20 Erase Timing Waveform SET-UP ERASE STANDSY AND COMMAND POWER UP RASURE AND STANDBY ERASE COMMAND el ERASE VERIFY COMMAND ERASE VERIFICATION POWER DOWN Address DATAPUMA 3F8003-15/17/20 MODULE DESCRIPTION When normal TTL/CMOS logic levels are applied to the Vpp Pin, the module displays normal EPROM Read, Standby, Output Disable and Device Identifier opera- tions. However, when high voltage (V,,,,) is applied to V,. the Write /Erase options are available as well as the Read. BUS OPERATIONS Read Two control functions are provided, both of which must be logically active to obtain data at the outputs. CS selects the module and controls the power, while OE gates data from the output pins - see the Read Cycle Timing Waveform for details. Write Module Write/Erasure are accessed via the command register while V,, is at Vpp,- Note that the register itself does not occupy an addressable memory location, but is simply a latch used to store the com- mand and address/data information required to ex- cecute the command. With CE and WE at V, the command register is ac- cessed; addresses are latched on the falling edge of ISSUE 1.0 : MARCH 1991 WE and data latched on the rising edge of WE. The three most significant register bits (D7- D5) encode the command function while all other bits (D4-D0) must be zero. The exception to this is the Reset command when data FF,, is written to the register and Identifier mode when 90,, is written to the register. Output Disable When OE is at V,,, the output pins are placed in a high impedance state and output from the module is disabled. Standby if CS is held at V,, the power consumption of the module is substantially reduced because most of the on-board circuitry is disabled. The outputs are placed in a high impedance state (independent of OE). if the PUMA 3F8003 module is deselected and placed in Standby mode during Write/Erase and Verify cycles, the module will continue to draw normal active current until the operation is terminated. Device Identifier Placing a high voltage (V,,) on pin A9 of the module causes the manufacturer and device codes to be output. This can be used to match the correct Write/Erase algorithms to the module. PUMA 3F8003 Bus Operations OPERATION Vpp"| ao | ag | GS | OF | WE | DO-D7 Read Vppp| AO | AD | Vi | Vi | Vin | Data out Output Disable Vept | X X | Vin | Vin | Vin. | Tri-State READ ONLY | Standby Vppt | X X | Vin | X X | Tri-State Manufacturer Identifier|Vpp. |V_ | Vio | Vie | Vic | Vin | Data = 89H Device Identifier Vee. | Vig | Vio | Vin | Vin | Vin | Data = BDH Read Vepy| AO | AQ | Va {Vi | Via | Data Out READ/WRITE Output Disable Vppy | X X | Va | Vin | Vin | Tri-State Standby Vppy| X X | Vin | X X | Tri-State Write Vepy| AO | AQ | Va | Vin | Vi. | Data in Notes (1) V,,, may be GND, a NC with a resistor tied to GND, or <V,,+2.0V. Vp,,, is the programming voltage specified for the device - refer to the DC Characteristics. When Vpp=Vpp, Memory contents can be read but not Written or Erased 2 0) addresses except AO and AQ must be at V,,. (3) 11.5V<V,, < 13.0V (4) (5) (5) Refer to Command Definition table for valid Data X can be V,, or Vier Manufacturer and Device codes may also be accessed via the command register. In this mode all Read operations with V,,=Vpp, May access array data or identifier codes (see page 7). {n during a Write operation.ISSUE 1.0 : MARCH 1991 COMMAND DEFINITIONS With the V,, pin at a low voltage the Command Register contents default to 00,,, enabling Read-only operations. A high voltage on V,, enable Read/Write modes with device operation selected by writing data into the Register - see the Command Definition table for details. Note that the following descriptions refer to the com- mands for the PUMA 3F8003 operating in 8 bit mode. The actual data presented to the module will change with the configured word width i.e. for the Erase Verify command of AO,,, if the PUMA is in 16 bit mode AOA0,, will be placed on the data bus and in 32 bit mode the data would be AOAOAOAO,.. Read While V,, is high the memory contents can be Read by first writing 00,, into the Command Register. A delay of 6ys is required before reading the first location, but all subsequent Read operations take t,,,. This mode remains enabled until the Command Register contents are altered. On power up theRegister contents will be 00,,, ensuring that the memory contents are not changed during the Vep/Veg Power transition. If the V,, pin is hard wired to a high voltage the memory will power up enabled for Read until the Register contents are altered. Intelligent Identifier _\n order to use the correct programming and erase algorithms on PROM devices, these parts usually have built in codes to identify manufacturer and specific device. However, to access these codes address line AQ has to be placed at a high voltage, which is not considered good practise and can lead to complications on PCB design. The PUMA 3F8003 module uses both of these codes to suppliment traditional PROM programming methodol- ogy, but the identifiers are accessed through the Command Register without placing a high voltage on AQ. Writing 90,, into the Register starts this process with a subsequent Read from 00000,, retrieving the manu- facturer code of 89,, and a Read from 00001,, giving the device code B4,,. To terminate this sequence another valid command must be written to the Register. Set-up Program/Program Set-up programis a com- mand only operation which prepares the memory for byte programming, initiated by writing 40,, into the command register. Once Set-up program has been performed, the next WE pulse causes data to be latched on the rising edge and the address is latched on the falling edge of this pulse. Internal programming begins on the rising edge and is terminated with the next rising edge of Write Enable used to write the program-verify command. PUMA 3F8003-15/17/20 Program-Verify This module is programmed byte by byte, which can occur sequentially or at random, but the byte just written must be verified. Writing CO,, to the command register begins this opera- tion, which also terminates the programming operation. The last byte written will be verified; no new address information is required as the previous address is latched. A Read Cycle can now be performed in order to compare the data just written with the byte contents. This process is shown by the Programming Algorithm. Set-up Erase/Erase Set-up erase isa command only operation which prepares the memory for electrical era- sure of all contents, initiated by writing 20,, to the Command Register. In order to start erasure 20,, must again be written to the register; this two-step sequence ensures that acciden- tal erasure will not occur. Additionally, if the V., pin is not at a high voltage the memory contents are protected against erasure. Erase-Verify The Erase command erases ail the contents of the memory, but after this operation all bytes must be verified. This is accomplished by writing A0,, to the Command Register, with the address of the byte to be verified supplied as it is latched on the falling edge of the Write-Enable pulse. Reading FF, from the addressed byte indicates that it is erased. This com- mand must be issued prior to each byte verification to latch its address. If the data read is not FF,, another erase operation must be performed. Verification can then continue from the address of the last verified byte, and once all bytes have been verified the erase procedure is complete. This process is shown by the Erase algorithm. The verify operation is halted by writing another valid command e.g. Set-up Program, into the command register. Reset This command, which consists of two consecu- tive writes of FF,, will safely abort either Erase or Program operations after the Set-up commands. Memory contents will not be altered, and a valid com- mand must then be written to place the device in the desired state. ALGORITHM NOTES It can be seen that the Programming and Erase algo- rithms both terminate with the Command Register being loaded with a Read command. If devices on the PUMA 3F8003 are being Programmed/Erased se- quentially (i.e. it is configured in 8 bit mode) then at the termination of the sequence all devices which have been accessed must be returned to the Read mode before correct operation can resume.PUMA 3F8003-15/17/20 ISSUE 1.0 : MARCH 1991 PUMA 3F8003 Command Definitions Bus First Bus Cycle Second Bus Cycle COMMAND deq'd |Operation | Addr | pata |operation | Addr | pata Read Memory) 1 Write X 001, Read RA | RD Read Identifier Code* 2 Write X 904 Read iA ID Set-up Erase/Erase 2 Write X 20, Write x 204 Erase Verify 2 Write EA | AO, Read x EVD Set-up Program/Program| 2 Write 4 404, Write PA PD Program Verify 2 Write x COy Read X PVD Reset ) 2 Write x FF, Write X FF, Notes (1) See Bus Operations Table. (2) IA = Identifier address. 00,, for Manufacturers code and 01,, for device code. EA = Address of memory location to be read during Erase Verify. PA. = Address of memory location to be programmed. RA_ = Address of memory location to be Read. Addresses are latched on the falling edge of Write Enable pulse. ID EVD = Data read from location EA during Erase (3) = Data read from location IA during device identification. (Manufacturer = 89,, Device = BD,,) Verify. PD = Data to be programmed at location PA. Data is latched on the rising edge of Write Enable. RD = Data to be read from location RA during Read operation. PVD = Data to be read from location PA during Program Verify. PA is latched on the Program command. (4) (5) (6) (7) (8) See the Erase Algorithm. See the Programming Algorithm. command, all subsequent Read operations take Parallel Erase \f the PUMA 2F800% is used in 16 or 32 bit mode then two or four devices will be accessed simultaneously. This reduces the total Erase time, but because individual devices will erase at different rates care must be taken that each device is verified sepa- rately. When a device is completely erased and verified a masking code should be used to prevent further erasur 6.g. writing the Read Command to the appro- priate device. Any other devices will continue to Erase until verified. Timing Delays Four timing delays are associated with the Program and Erase algorithms described: (1) When V,, first tums on the capacitors on the V,, line cause an RC ramp, the rise time of which is propor- tional to the number of devices being erased and the capacitance per device. V,, must reach its final value 100ns before any commands are excecuted. (2) The second timing delay is the erase time pulse width of 10ms, which should be timed by a routine run by the local microprocessor. This operation must be terminated before servicing any system interrupts which may occur during the routine. An Erase/Verify command should be written after each Following the Read Identifier command, two read operations access the manufacturer and device codes. The second bus cycle must be followed by the desired command register write. Wait 6ys after the first Read command before accessing data. When the second bus command is a Read face? erase pulse, otherwise the device(s) may continue to erase until the memory cells are driven into depletion. A symptom of this over erasure is an error attempting to Write the next time; occasionally it may be possible to recover this situation by programming all of the locations with 00,,. Each Write pulse width is 10s, and since the algorithm is interactive each byte is verified after a Write pulse. The program operation must be termi- nated at the conclusion of the timing routine or prior to sevicing any interrupts which may occur during this operation. A fourth delay is associated with both the Write and Erase algorithms is the Write recovery time of 6s. In order to improve memory cell operation, an internally generated margin voltage is applied to the addressed cell during Write/Erase Verify. It is during this 6us delay that the internal circuitry is changing voltage levels between the Erase/Write level and those used for Verify and Read opera- tions. Any attempt to Read the device(s) during this period will result in possible false data appearing on the outputs. (3) (4)ISSUE 1.0 : MARCH 1991 PUMA 3F8003-15/17/20 PROGRAMMING ALGORITHM ERASE ALGORITHM These algorithms MUST BE FOLLOWED to ensure proper and reliable operation, and are shown for a single device only. WRITE SET-UP PROGRAM CMD v WRITE PROGRAM CMD (A/D) TIME OUT 10 ps WRITE PROGRAM VERIFY CMD v READ DATA FROM DEVICE INCREMENT ADDRESS LAST ADDRESS YES WRITE READ CMD | APPLY Ver) | APPLY Vppi") v ( FRocRaM ] [ PROGRAM COMPLETE ERROR: Notes (1) See DC Characteristics for the value of V,.,,. The V,, supply can be hard wired to the device or switchable.When V,,, is switched, Vop, May be GND, NC with a resistor tied to GND or less than Voet2.0V "START -ERASURE SELECT DEVICE PROGRAM ALL BYTES TO 00H v APPLY VepH'?) ADDR = 00H PLSCNT = 0 at. v WRITE ERASE SET-UP CMD ' WRITE ERASE CMD TIME OUT 10 ms a INCREMENT ADDRESS y WRITE ERASE VERIFY CMD TIME OUT 6 ps READ DATA FROM DEVICE YE: T LAS ADDRESS $ YES WRITE READ CMD [APPLY Verc | | APPLY Veet ERASURE COMPLETE ERASE ERROR 10PUMA 3F8003-15/17/20 DESIGN CONSIDERATIONS Two Line Control Two Read signals are provided for output control to accommodate large memory arrays, giving the lowest possible memory power dissipation and ensuring bus contention does not occur. To use this feature efficiently, an address decoder output should drive the CS line while the system read signal controls all memories in parallel. This ensures that only enabled memories have active outputs and deselected devices are in the low power Standby con- dition. Supply Decoupling Flash memory power-switching characteristics require careful decoupling. Three sup- ply current issues have to be considered - Standby, Active and transient current peaks caused by rising and falling edges of CS. Two line control and correct decoupling capacitor se- lection will help to suppress these transient voltage peaks. This module has three on-board decoupling ca- pacitors of 0.1F connected between V,,. and GND. Additionally, a 0.1uF or larger capacitor should be placed close to the module between V,, and GND. ISSUE 1.0 : MARCH 1991 It is recommended that a 4.74F electrolytic capacitor should be placed between V,,. and GND every two PUMA 3F8003 modules. This capacitor will smooth out voltage dips in the supply caused by PCB track induc- tance and will supply charge to the onboard capacitors as needed. V,, Trace Because Flash memories are designed to be programmed in situ, the PCB designer must be made aware of the V,, supply trace. This should be made similar to the V,,, bus as the V,,, pin supplies the memory cell current for Programming and Erase. Power Up/Down _ This Flash module is protected against accidental writes caused by power transitions, powering up in the Read only mode. Additionally, by using two step command register sequences this pro- tection is further enhanced. While these functions are sufficient in most cases, it is recommended that V,, should reach a steady state value before V,, is greater than V,.+2.0V, and during power down V,,, should be less than V,,.+2.0V before lowering V,-. Connection Table PGA | Signal | PGA | Signal | PGA | Signal | PGA | Signal | PGA | Signal Pin No.| Name Pin No. | - Name Pin No. | Name Pin No.| Name Pin No.| Name 1 | Se 2 D9 3 D10 4 Al4 5 | A16 6 Alt 7 AO 8 NC 9 DO 10 D1 11 D2 12 WE2 13 C82 14 GND 15 D11 16 A10 17 AQ 18 A15 19 Voc 20 | CS1 21 NC 22 D3 23 D15 24 D14 25 D13 26 D12 27 OE 28 A17 29 WE1 30 D7 31 D6 32 DS 33 D4 34 024 35 D25 36 D26 37 AT 38 Al2 39 Vow 40 A13 Al A8 42 D16 43 D17 44 D18 45 Voc 46 CS4 47 WE4 48 D27 49 A4 50 AS 51 AG 52 WES 53 CS3 54 GND 55 | D19 56 D31 57 p30 | 58 p29 59 D28 60 At 61 A2 62 A3 63 D23 64 D22 65 D21 66 D20 11ISSUE 1.0 : MARCH 1991 PUMA 3F8003-15/17/20 Ordering Information PUMA 3F8003!I-20 LIL J Speed 15 = 150 ns (see note below) 17 = 170 ns 20 = 200 ns Temperature range Blank = Commercial Temperature I = Industrial Temperature Organisation 8003 = 8Mbit array, configurable as 256K x 32 bit or 512K x 16 bit or 1024K x 8 bit Technology 3F = FLASH MEMORY on PUMA Plastic substrate NOTE: The PUMA 3F8003!-15 module is currently in development and is not available at the present time. motaic Mosaic Semiconductor The policy of the company is one of continuous development and while the information presented in this data sheet is me believed to be accurate, no liability is assumed for any data contained within. The company reserves the right to make 7420 Carroll Road changes without notice at any time. San Diego, CA 92121 Tel: (619) 271 4565 FAX: (619) 274 6058 ozsa7a YX 1988 This design is the property of Mosaic Semiconductor, Inc. | 2%